Initial commit: CCU621_M firmware project with BLE debug link support.
Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
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/*!
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\file gd32h7xx_hau.h
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\brief definitions for the HAU
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\version 2025-01-24, V1.4.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H7XX_HAU_H
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#define GD32H7XX_HAU_H
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#include "gd32h7xx.h"
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/* HAU definitions */
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#define HAU HAU_BASE
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/* registers definitions */
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#define HAU_CTL REG32(HAU + 0x00000000U) /*!< control register */
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#define HAU_DI REG32(HAU + 0x00000004U) /*!< data input register */
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#define HAU_CFG REG32(HAU + 0x00000008U) /*!< configuration register */
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#define HAU_DO0 REG32(HAU + 0x0000000CU) /*!< data output register 0 */
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#define HAU_DO1 REG32(HAU + 0x00000010U) /*!< data output register 1 */
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#define HAU_DO2 REG32(HAU + 0x00000014U) /*!< data output register 2 */
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#define HAU_DO3 REG32(HAU + 0x00000018U) /*!< data output register 3 */
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#define HAU_DO4 REG32(HAU + 0x0000001CU) /*!< data output register 4 */
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#define HAU_DO5 REG32(HAU + 0x00000324U) /*!< data output register 5 */
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#define HAU_DO6 REG32(HAU + 0x00000328U) /*!< data output register 6 */
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#define HAU_DO7 REG32(HAU + 0x0000032CU) /*!< data output register 7 */
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#define HAU_INTEN REG32(HAU + 0x00000020U) /*!< interrupt enable register */
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#define HAU_STAT REG32(HAU + 0x00000024U) /*!< status and interrupt flag register */
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#define HAU_CTXS(x) REG32(HAU + 0x000000F8U + 0x04U * (x)) /*!< context switch register x, x <= 53 */
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/* bits definitions */
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/* HAU_CTL */
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#define HAU_CTL_START BIT(2) /*!< set to 1 to reset the HAU processor core, so that it is ready to start the digest calculation */
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#define HAU_CTL_DMAE BIT(3) /*!< DMA enable */
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#define HAU_CTL_DATAM BITS(4,5) /*!< data type mode */
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#define HAU_CTL_HMS BIT(6) /*!< HAU mode selection */
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#define HAU_CTL_ALGM_0 BIT(7) /*!< algorithm selection bit 0 */
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#define HAU_CTL_NWIF BITS(8,11) /*!< number of words in the input FIFO */
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#define HAU_CTL_DINE BIT(12) /*!< DI register not empty */
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#define HAU_CTL_MDS BIT(13) /*!< multiple DMA selection */
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#define HAU_CTL_KLM BIT(16) /*!< key length mode */
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#define HAU_CTL_ALGM_1 BIT(18) /*!< algorithm selection bit 1 */
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/* HAU_DI */
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#define HAU_DI_DI BITS(0,31) /*!< message data input */
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/* HAU_CFG */
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#define HAU_CFG_VBL BITS(0,4) /*!< valid bits length in the last word */
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#define HAU_CFG_CALEN BIT(8) /*!< digest calculation enable */
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/* HAU_DOx x=0..7 */
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#define HAU_DOX_DOX BITS(0,31) /*!< message digest result of hash algorithm */
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/* HAU_INTEN */
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#define HAU_INTEN_DIIE BIT(0) /*!< data input interrupt enable */
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#define HAU_INTEN_CCIE BIT(1) /*!< calculation completion interrupt enable */
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/* HAU_STAT */
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#define HAU_STAT_DIF BIT(0) /*!< data input interrupt flag */
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#define HAU_STAT_CCF BIT(1) /*!< digest calculation completion interrupt flag */
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#define HAU_STAT_DMAS BIT(2) /*!< DMA status */
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#define HAU_STAT_BUSY BIT(3) /*!< busy bit */
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/* constants definitions */
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/* structure for initialization of the hau */
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typedef struct
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{
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uint32_t algo; /*!< algorithm selection */
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uint32_t mode; /*!< HAU mode selection */
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uint32_t datatype; /*!< data type mode */
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uint32_t keytype; /*!< key length mode */
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}hau_init_parameter_struct;
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/* structure for message digest result of the hau */
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typedef struct
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{
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uint32_t out[8]; /*!< message digest result 0-7 */
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}hau_digest_parameter_struct;
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/* structure for context switch */
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typedef struct
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{
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uint32_t hau_ctl_bak; /*!< backup of HAU_CTL register */
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uint32_t hau_cfg_bak; /*!< backup of HAU_CFG register */
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uint32_t hau_inten_bak; /*!< backup of HAU_INTEN register */
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uint32_t hau_ctxs_bak[54]; /*!< backup of HAU_CTXSx registers */
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}hau_context_parameter_struct;
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/* hau_ctl register value */
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#define HAU_ALGO_SHA1 ((uint32_t)0x00000000U) /*!< HAU function is SHA1 */
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#define HAU_ALGO_SHA224 HAU_CTL_ALGM_1 /*!< HAU function is SHA224 */
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#define HAU_ALGO_SHA256 (HAU_CTL_ALGM_1 | HAU_CTL_ALGM_0) /*!< HAU function is SHA256 */
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#define HAU_ALGO_MD5 HAU_CTL_ALGM_0 /*!< HAU function is MD5 */
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#define HAU_MODE_HASH ((uint32_t)0x00000000U) /*!< HAU mode is HASH */
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#define HAU_MODE_HMAC HAU_CTL_HMS /*!< HAU mode is HMAC */
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#define CTL_DATAM_1(regval) (BITS(4,5) & ((uint32_t)(regval) << 4U)) /*!< write value to HAU_CTL_DATAM bit field */
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#define HAU_SWAPPING_32BIT CTL_DATAM_1(0) /*!< no swapping */
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#define HAU_SWAPPING_16BIT CTL_DATAM_1(1) /*!< half-word swapping */
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#define HAU_SWAPPING_8BIT CTL_DATAM_1(2) /*!< bytes swapping */
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#define HAU_SWAPPING_1BIT CTL_DATAM_1(3) /*!< bit swapping */
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#define HAU_KEY_SHORTER_64 ((uint32_t)0x00000000U) /*!< HMAC key is <= 64 bytes */
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#define HAU_KEY_LONGGER_64 HAU_CTL_KLM /*!< HMAC key is > 64 bytes */
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#define GET_CTL_NWIF(regval) GET_BITS((regval),8,11) /*!< get value of HAU_CTL_NWIF bit field */
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#define SINGLE_DMA_AUTO_DIGEST ((uint32_t)0x00000000U) /*!< message padding and message digest calculation at the end of a DMA transfer */
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#define MULTIPLE_DMA_NO_DIGEST HAU_CTL_MDS /*!< multiple DMA transfers needed and CALEN bit is not automatically set at the end of a DMA transfer */
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/* hau_cfg register value */
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#define CFG_VBL(regval) (BITS(0,4) & (((uint32_t)(regval)))) /*!< write value to HAU_CFG_VBL bit field */
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/* hau_inten register value */
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#define HAU_INT_DATA_INPUT HAU_INTEN_DIIE /*!< a new block can be entered into the IN buffer */
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#define HAU_INT_CALCULATION_COMPLETE HAU_INTEN_CCIE /*!< calculation complete */
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#define HAU_FLAG_DATA_INPUT HAU_STAT_DIF /*!< there is enough space (16 bytes) in the input FIFO */
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#define HAU_FLAG_CALCULATION_COMPLETE HAU_STAT_CCF /*!< digest calculation is completed */
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#define HAU_FLAG_DMA HAU_STAT_DMAS /*!< DMA is enabled (DMAE =1) or a transfer is processing */
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#define HAU_FLAG_BUSY HAU_STAT_BUSY /*!< data block is in process */
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#define HAU_FLAG_INFIFO_NO_EMPTY HAU_CTL_DINE /*!< the input FIFO is not empty */
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#define HAU_INT_FLAG_DATA_INPUT HAU_STAT_DIF /*!< there is enough space (16 bytes) in the input FIFO */
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#define HAU_INT_FLAG_CALCULATION_COMPLETE HAU_STAT_CCF /*!< digest calculation is completed */
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/* function declarations */
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/* initialization functions */
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/* reset the HAU peripheral */
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void hau_deinit(void);
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/* initialize the HAU peripheral parameters */
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void hau_init(hau_init_parameter_struct* initpara);
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/* initialize the structure hau_initpara with default value */
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void hau_init_struct_para_init(hau_init_parameter_struct* initpara);
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/* reset the HAU processor core */
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void hau_reset(void);
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/* configure the number of valid bits in last word of the message */
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void hau_last_word_validbits_num_config(uint32_t valid_num);
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/* write data to the IN FIFO */
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void hau_data_write(uint32_t data);
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/* return the number of words already written into the IN FIFO */
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uint32_t hau_infifo_words_num_get(void);
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/* read the message digest result */
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void hau_digest_read(hau_digest_parameter_struct* digestpara);
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/* enable digest calculation */
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void hau_digest_calculation_enable(void);
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/* configure single or multiple DMA is used, and digest calculation at the end of a DMA transfer or not */
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void hau_multiple_single_dma_config(uint32_t multi_single);
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/* enable the HAU DMA interface */
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void hau_dma_enable(void);
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/* disable the HAU DMA interface */
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void hau_dma_disable(void);
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/* context swapping functions */
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/* initialize the struct context */
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void hau_context_struct_para_init(hau_context_parameter_struct* context);
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/* save the HAU peripheral context */
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void hau_context_save(hau_context_parameter_struct* context_save);
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/* restore the HAU peripheral context */
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void hau_context_restore(hau_context_parameter_struct* context_restore);
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/* calculate digest in HASH mode */
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/* calculate digest using SHA1 in HASH mode */
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ErrStatus hau_hash_sha_1(uint8_t input[], uint32_t in_length, uint8_t output[]);
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/* calculate digest using SHA1 in HMAC mode */
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ErrStatus hau_hmac_sha_1(uint8_t key[], uint32_t keysize, uint8_t input[], uint32_t in_length, uint8_t output[]);
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/* calculate digest using SHA224 in HASH mode */
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ErrStatus hau_hash_sha_224(uint8_t input[], uint32_t in_length, uint8_t output[]);
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/* calculate digest using SHA224 in HMAC mode */
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ErrStatus hau_hmac_sha_224(uint8_t key[], uint32_t keysize, uint8_t input[], uint32_t in_length, uint8_t output[]);
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/* calculate digest using SHA256 in HASH mode */
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ErrStatus hau_hash_sha_256(uint8_t input[], uint32_t in_length, uint8_t output[]);
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/* calculate digest using SHA256 in HMAC mode */
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ErrStatus hau_hmac_sha_256(uint8_t key[], uint32_t keysize, uint8_t input[], uint32_t in_length, uint8_t output[]);
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/* calculate digest using MD5 in HASH mode */
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ErrStatus hau_hash_md5(uint8_t input[], uint32_t in_length, uint8_t output[]);
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/* calculate digest using MD5 in HMAC mode */
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ErrStatus hau_hmac_md5(uint8_t key[], uint32_t keysize, uint8_t input[], uint32_t in_length, uint8_t output[]);
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/* interrupt & flag functions */
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/* get the HAU flag status */
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FlagStatus hau_flag_get(uint32_t flag);
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/* clear the HAU flag status */
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void hau_flag_clear(uint32_t flag);
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/* enable the HAU interrupts */
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void hau_interrupt_enable(uint32_t interrupt);
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/* disable the HAU interrupts */
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void hau_interrupt_disable(uint32_t interrupt);
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/* get the HAU interrupt flag status */
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FlagStatus hau_interrupt_flag_get(uint32_t int_flag);
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/* clear the HAU interrupt flag status */
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void hau_interrupt_flag_clear(uint32_t int_flag);
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#endif /* GD32H7XX_HAU_H */
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