Initial commit: CCU621_M firmware project with BLE debug link support.
Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
@@ -0,0 +1,693 @@
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/*!
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\file gd32h7xx_spi.h
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\brief definitions for the SPI
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\version 2025-01-24, V1.4.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H7XX_SPI_H
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#define GD32H7XX_SPI_H
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#include "gd32h7xx.h"
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/* SPIx(x=0,1,2,3,4,5) definitions */
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#define SPI0 (SPI_BASE + 0x0000F800U)
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#define SPI1 SPI_BASE
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#define SPI2 (SPI_BASE + 0x00000400U)
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#define SPI3 (SPI_BASE + 0x0000FC00U)
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#define SPI4 (SPI_BASE + 0x00011800U)
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#define SPI5 (SPI_BASE + 0x00010000U)
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/* SPI registers definitions */
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#define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */
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#define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/
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#define SPI_CFG0(spix) REG32((spix) + 0x08U) /*!< SPI configuration register 0 */
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#define SPI_CFG1(spix) REG32((spix) + 0x0CU) /*!< SPI configuration register 1 */
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#define SPI_INT(spix) REG32((spix) + 0x10U) /*!< SPI interrupt register */
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#define SPI_STAT(spix) REG32((spix) + 0x14U) /*!< SPI status register */
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#define SPI_STATC(spix) REG32((spix) + 0x18U) /*!< SPI interrupt/status flags clear register */
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#define SPI_TDATA(spix) REG32((spix) + 0x20U) /*!< SPI data transfer register */
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#define SPI_RDATA(spix) REG32((spix) + 0x30U) /*!< SPI data receive register */
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#define SPI_CRCPOLY(spix) REG32((spix) + 0x40U) /*!< SPI CRC polynomial register */
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#define SPI_TCRC(spix) REG32((spix) + 0x44U) /*!< SPI TX CRC register */
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#define SPI_RCRC(spix) REG32((spix) + 0x48U) /*!< SPI RX CRC register */
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#define SPI_URDATA(spix) REG32((spix) + 0x4CU) /*!< SPI underrun data register */
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#define SPI_I2SCTL(spix) REG32((spix) + 0x50U) /*!< I2S control register */
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#define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< quad_SPI mode control register(for SPI3/4) */
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#define SPI_RXDLYCK(spix) REG32((spix) + 0xFCU) /*!< SPI receive clock delay register */
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/* bits definitions */
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/* SPI_CTL0 */
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#define SPI_CTL0_SPIEN BIT(0) /*!< SPI enable */
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#define SPI_CTL0_MASP BIT(8) /*!< the master is suspended automatically in receive mode */
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#define SPI_CTL0_MSTART BIT(9) /*!< master start transfer */
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#define SPI_CTL0_MSPDR BIT(10) /*!< suspend request in SPI master mode */
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#define SPI_CTL0_NSSI BIT(12) /*!< the input level to internal NSS signal */
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#define SPI_CTL0_CRCFS BIT(13) /*!< full scale CRC polynomial configuration */
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#define SPI_CTL0_RXCRCI BIT(14) /*!< the receiver CRC initialization configuration */
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#define SPI_CTL0_TXCRCI BIT(15) /*!< the transmitter CRC initialization configuration */
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#define SPI_CTL0_IOAFEN BIT(16) /*!< related IOs AF configuration enable */
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/* SPI_CFG0 */
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#define SPI_CFG0_DZ BITS(0,4) /*!< data size */
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#define SPI_CFG0_FIFOLVL BITS(5,8) /*!< FIFO threshold level */
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#define SPI_CFG0_TXUROP BITS(9,10) /*!< operation of slave transmitter when underrun detected */
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#define SPI_CFG0_TXURDT BITS(11,12) /*!< detection of underrun error at slave transmitter */
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#define SPI_CFG0_DMAREN BIT(14) /*!< receive buffer DMA enable */
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#define SPI_CFG0_DMATEN BIT(15) /*!< transmit buffer DMA enable */
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#define SPI_CFG0_CRCSZ BITS(16,20) /*!< CRC size */
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#define SPI_CFG0_CRCEN BIT(22) /*!< CRC calculation enable */
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#define SPI_CFG0_BYTEN BIT(23) /*!< byte access enable */
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#define SPI_CFG0_WORDEN BIT(24) /*!< word access enable */
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#define SPI_CFG0_PSC BITS(28,30) /*!< master clock prescaler selection */
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/* SPI_CFG1 */
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#define SPI_CFG1_MSSD BITS(0,3) /*!< delay between active edge of NSS and start transfer or receive data in SPI master mode */
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#define SPI_CFG1_MDFD BITS(4,7) /*!< delay between the data frames in SPI master mode */
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#define SPI_CFG1_SWPMIO BIT(15) /*!< MOSI and MISO pin swap */
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#define SPI_CFG1_RO BIT(16) /*!< receive only */
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#define SPI_CFG1_BDOEN BIT(17) /*!< bidirectional transmit output enable */
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#define SPI_CFG1_BDEN BIT(18) /*!< bidirectional enable */
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#define SPI_CFG1_TMOD BIT(21) /*!< SPI TI mode enable */
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#define SPI_CFG1_MSTMOD BIT(22) /*!< Master mode enable */
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#define SPI_CFG1_LF BIT(23) /*!< LSB first mode */
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#define SPI_CFG1_CKPH BIT(24) /*!< clock phase selection */
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#define SPI_CFG1_CKPL BIT(25) /*!< clock polarity selection */
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#define SPI_CFG1_NSSIM BIT(26) /*!< NSS input signal manage mode */
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#define SPI_CFG1_NSSIOPL BIT(28) /*!< NSS pin input/output polarity selection */
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#define SPI_CFG1_NSSDRV BIT(29) /*!< NSS pin output enable in master mode */
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#define SPI_CFG1_NSSCTL BIT(30) /*!< NSS pin output control in master mode */
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#define SPI_CFG1_AFCTL BIT(31) /*!< AF GPIOs control */
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/* SPI_INT */
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#define SPI_INT_RPIE BIT(0) /*!< RP interrupt enable */
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#define SPI_INT_TPIE BIT(1) /*!< TP interrupt enable */
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#define SPI_INT_DPIE BIT(2) /*!< DP interrupt enable */
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#define SPI_INT_ESTCIE BIT(3) /*!< end of transfer or suspend or TXFIFO clear interrupt enable */
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#define SPI_INT_TXFIE BIT(4) /*!< transmission filled interrupt enable */
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#define SPI_INT_TXUREIE BIT(5) /*!< underrun error interrupt enable */
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#define SPI_INT_RXOREIE BIT(6) /*!< overrun error interrupt enable */
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#define SPI_INT_CRCERIE BIT(7) /*!< CRC error interrupt enable */
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#define SPI_INT_FEIE BIT(8) /*!< TI frame error interrupt enable */
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#define SPI_INT_CONFEIE BIT(9) /*!< SPI configuration error interrupt enable */
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#define SPI_INT_TXSERFIE BIT(10) /*!< TXSER reload interrupt enable */
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/* SPI_STAT */
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#define SPI_STAT_RP BIT(0) /*!< RxFIFO packet space available flag */
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#define SPI_STAT_TP BIT(1) /*!< TxFIFO packet space available flag */
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#define SPI_STAT_DP BIT(2) /*!< duplex packet */
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#define SPI_STAT_ET BIT(3) /*!< End of transmission/reception flag */
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#define SPI_STAT_TXF BIT(4) /*!< TxFIFO transmission has been filled */
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#define SPI_STAT_TXURERR BIT(5) /*!< transmission underrun error */
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#define SPI_STAT_RXORERR BIT(6) /*!< reception overrun error */
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#define SPI_STAT_CRCERR BIT(7) /*!< SPI CRC error */
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#define SPI_STAT_FERR BIT(8) /*!< SPI TI format error */
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#define SPI_STAT_CONFERR BIT(9) /*!< SPI configuration error */
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#define SPI_STAT_TXSERF BIT(10) /*!< The additional SPI data has been reloaded */
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#define SPI_STAT_SPD BIT(11) /*!< suspend flsg */
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#define SPI_STAT_TC BIT(12) /*!< TxFIFO transmission complete flag */
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#define SPI_STAT_RPLVL BITS(13,14) /*!< RxFIFO packing level */
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#define SPI_STAT_RWNE BIT(15) /*!< the word of RXFIFO is not empty */
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#define SPI_STAT_CTXSIZE BITS(16,31) /*!< the number of data frames remaining in the TXSIZE session */
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/* SPI_STATC */
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#define SPI_STATC_ETC BIT(3) /*!< Clear the end of transmission/reception flag */
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#define SPI_STATC_TXFC BIT(4) /*!< Clear the TxFIFO transmission filled flag */
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#define SPI_STATC_TXURERRC BIT(5) /*!< clear the transmission underrun error flag */
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#define SPI_STATC_RXORERRC BIT(6) /*!< clear the reception overrun error flag */
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#define SPI_STATC_CRCERRC BIT(7) /*!< clear the CRC error flag */
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#define SPI_STATC_FERRC BIT(8) /*!< clear the SPI TI format error flag */
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#define SPI_STATC_CONFERRC BIT(9) /*!< clear the configuration error flag */
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#define SPI_STATC_TXSERFC BIT(10) /*!< clear the TXSERF flag */
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#define SPI_STATC_SPDC BIT(11) /*!< clear the suspend flag */
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/* SPI_TDATA */
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#define SPI_TDATA_TDATA BITS(0,31) /*!< data transfer register */
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/* SPI_RDATA */
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#define SPI_RDATA_RDATA BITS(0,31) /*!< data receive register */
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/* SPI_CRCPOLY */
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#define SPI_CRCPOLY_CRCPOLY BITS(0,31) /*!< CRC polynomial register */
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/* SPI_TCRC */
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#define SPI_TCRC_TCRC BITS(0,31) /*!< Tx CRC register */
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/* SPI_RCRC */
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#define SPI_RCRC_RCRC BITS(0,31) /*!< Rx CRC register */
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/* SPI_URDATA */
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#define SPI_URDATA_URDATA BITS(0,31) /*!< transmission underrun data at slave mode */
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/* SPI_I2SCTL */
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#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
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#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
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#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
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#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
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#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
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#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
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#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
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#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
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#define SPI_I2SCTL_DIV BITS(16,23) /*!< dividing factor for the prescaler */
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#define SPI_I2SCTL_OF BIT(24) /*!< odd factor for the prescaler */
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#define SPI_I2SCTL_MCKOEN BIT(25) /*!< I2S_MCK output enable */
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#define SPI_I2SCTL_I2SCH BIT(31) /*!< I2S Channel side */
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/* SPI_QCTL(only for SPI3/4) */
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#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */
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#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */
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#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */
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/* SPI_RXDLYCK */
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#define SPI_RXDLYCK_SRXD BITS(0,4) /*!< slave mode receive clock delay units*/
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#define SPI_RXDLYCK_SRXDEN BIT(5) /*!< slave mode receive clock delay enable*/
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#define SPI_RXDLYCK_MRXD BITS(6,10) /*!< master mode receive clock delay units*/
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#define SPI_RXDLYCK_MRXDEN BIT(11) /*!< master mode receive clock delay enable*/
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/* constants definitions */
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/* SPI and I2S parameter struct definitions */
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typedef struct
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{
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uint32_t device_mode; /*!< SPI master or slave */
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uint32_t trans_mode; /*!< SPI transtype */
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uint32_t data_size; /*!< SPI data frame size */
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uint32_t nss; /*!< SPI NSS control by handware or software */
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uint32_t endian; /*!< SPI big endian or little endian */
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uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
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uint32_t prescale; /*!< SPI prescale factor */
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}spi_parameter_struct;
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/* SPI suspend in receive mode */
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#define SPI_AUTO_SUSPEND SPI_CTL0_MASP /*!< until the overrun condition is reached, the SPI stream is suspended in the full RxFIFO state */
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#define SPI_CONTINUOUS ((uint32_t)0x00000000U) /*!< SPI stream/clock generation is continuous whether or not an overrun occurs */
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/* SPI master start transfer */
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#define SPI_TRANS_START SPI_CTL0_MSTART /*!< the master transmission is occurring, or has been temporarily suspended by automatic suspend */
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#define SPI_TRANS_IDLE ((uint32_t)0x00000000U) /*!< the master transfer is idle status */
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/* SPI NSS input level */
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#define SPI_NSS_LEVEL_HIGH SPI_CTL0_NSSI /*!< NSS pin is pulled high */
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#define SPI_NSS_LEVEL_LOW ((uint32_t)0x00000000U) /*!< NSS pin is pulled low */
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/* SPI TCRC init pattern */
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#define SPI_TCRC_INIT_1 SPI_CTL0_TXCRCI /*!< use all 1 pattern */
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#define SPI_TCRC_INIT_0 ((uint32_t)0x00000000U) /*!< use all 0 pattern */
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/* SPI RCRC init pattern */
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#define SPI_RCRC_INIT_1 SPI_CTL0_RXCRCI /*!< use all 1 pattern */
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#define SPI_RCRC_INIT_0 ((uint32_t)0x00000000U) /*!< use all 0 pattern */
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/* SPI data frame size */
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#define CFG0_DZ(regval) (BITS(0,4) & ((uint32_t)(regval) << 0))
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#define SPI_DATASIZE_4BIT CFG0_DZ(3) /*!< SPI data frame size is 4-bit */
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#define SPI_DATASIZE_5BIT CFG0_DZ(4) /*!< SPI data frame size is 5-bit */
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#define SPI_DATASIZE_6BIT CFG0_DZ(5) /*!< SPI data frame size is 6-bit */
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#define SPI_DATASIZE_7BIT CFG0_DZ(6) /*!< SPI data frame size is 7-bit */
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#define SPI_DATASIZE_8BIT CFG0_DZ(7) /*!< SPI data frame size is 8-bit */
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#define SPI_DATASIZE_9BIT CFG0_DZ(8) /*!< SPI data frame size is 9-bit */
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#define SPI_DATASIZE_10BIT CFG0_DZ(9) /*!< SPI data frame size is 10-bit */
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#define SPI_DATASIZE_11BIT CFG0_DZ(10) /*!< SPI data frame size is 11-bit */
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#define SPI_DATASIZE_12BIT CFG0_DZ(11) /*!< SPI data frame size is 12-bit */
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#define SPI_DATASIZE_13BIT CFG0_DZ(12) /*!< SPI data frame size is 13-bit */
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#define SPI_DATASIZE_14BIT CFG0_DZ(13) /*!< SPI data frame size is 14-bit */
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#define SPI_DATASIZE_15BIT CFG0_DZ(14) /*!< SPI data frame size is 15-bit */
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#define SPI_DATASIZE_16BIT CFG0_DZ(15) /*!< SPI data frame size is 16-bit */
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#define SPI_DATASIZE_17BIT CFG0_DZ(16) /*!< SPI data frame size is 17-bit */
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#define SPI_DATASIZE_18BIT CFG0_DZ(17) /*!< SPI data frame size is 18-bit */
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#define SPI_DATASIZE_19BIT CFG0_DZ(18) /*!< SPI data frame size is 19-bit */
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#define SPI_DATASIZE_20BIT CFG0_DZ(19) /*!< SPI data frame size is 20-bit */
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#define SPI_DATASIZE_21BIT CFG0_DZ(20) /*!< SPI data frame size is 21-bit */
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#define SPI_DATASIZE_22BIT CFG0_DZ(21) /*!< SPI data frame size is 22-bit */
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#define SPI_DATASIZE_23BIT CFG0_DZ(22) /*!< SPI data frame size is 23-bit */
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#define SPI_DATASIZE_24BIT CFG0_DZ(23) /*!< SPI data frame size is 24-bit */
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#define SPI_DATASIZE_25BIT CFG0_DZ(24) /*!< SPI data frame size is 25-bit */
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#define SPI_DATASIZE_26BIT CFG0_DZ(25) /*!< SPI data frame size is 26-bit */
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#define SPI_DATASIZE_27BIT CFG0_DZ(26) /*!< SPI data frame size is 27-bit */
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#define SPI_DATASIZE_28BIT CFG0_DZ(27) /*!< SPI data frame size is 28-bit */
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#define SPI_DATASIZE_29BIT CFG0_DZ(28) /*!< SPI data frame size is 29-bit */
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#define SPI_DATASIZE_30BIT CFG0_DZ(29) /*!< SPI data frame size is 30-bit */
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#define SPI_DATASIZE_31BIT CFG0_DZ(30) /*!< SPI data frame size is 31-bit */
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#define SPI_DATASIZE_32BIT CFG0_DZ(31) /*!< SPI data frame size is 32-bit */
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/* SPI FIFO threshold level */
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#define CFG0_FIFOLVL(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
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#define SPI_FIFO_TH_01DATA CFG0_FIFOLVL(0) /*!< set FIFO threshold level = 1-data frame */
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#define SPI_FIFO_TH_02DATA CFG0_FIFOLVL(1) /*!< set FIFO threshold level = 2-data frame */
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#define SPI_FIFO_TH_03DATA CFG0_FIFOLVL(2) /*!< set FIFO threshold level = 3-data frame */
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#define SPI_FIFO_TH_04DATA CFG0_FIFOLVL(3) /*!< set FIFO threshold level = 4-data frame */
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#define SPI_FIFO_TH_05DATA CFG0_FIFOLVL(4) /*!< set FIFO threshold level = 5-data frame */
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#define SPI_FIFO_TH_06DATA CFG0_FIFOLVL(5) /*!< set FIFO threshold level = 6-data frame */
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#define SPI_FIFO_TH_07DATA CFG0_FIFOLVL(6) /*!< set FIFO threshold level = 7-data frame */
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#define SPI_FIFO_TH_08DATA CFG0_FIFOLVL(7) /*!< set FIFO threshold level = 8-data frame */
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#define SPI_FIFO_TH_09DATA CFG0_FIFOLVL(8) /*!< set FIFO threshold level = 9-data frame */
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#define SPI_FIFO_TH_10DATA CFG0_FIFOLVL(9) /*!< set FIFO threshold level = 10-data frame */
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#define SPI_FIFO_TH_11DATA CFG0_FIFOLVL(10) /*!< set FIFO threshold level = 11-data frame */
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#define SPI_FIFO_TH_12DATA CFG0_FIFOLVL(11) /*!< set FIFO threshold level = 12-data frame */
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#define SPI_FIFO_TH_13DATA CFG0_FIFOLVL(12) /*!< set FIFO threshold level = 13-data frame */
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#define SPI_FIFO_TH_14DATA CFG0_FIFOLVL(13) /*!< set FIFO threshold level = 14-data frame */
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#define SPI_FIFO_TH_15DATA CFG0_FIFOLVL(14) /*!< set FIFO threshold level = 15-data frame */
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#define SPI_FIFO_TH_16DATA CFG0_FIFOLVL(15) /*!< set FIFO threshold level = 16-data frame */
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/* SPI slave transmitter underrun detected operation */
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#define CFG0_TXUROP(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
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#define SPI_CONFIG_REGISTER_PATTERN CFG0_TXUROP(0) /*!< slave send a constant value defined by the SPI_URDATA register */
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#define SPI_CONFIG_LAST_RECEIVED CFG0_TXUROP(1) /*!< slave send the data frame received from master lastly */
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#define SPI_CONFIG_LAST_TRANSMITTED CFG0_TXUROP(2) /*!< Slave send the data frame which is lastly transmitted by itself */
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/* SPI slave transmitter underrun detected config */
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#define CFG0_TXURDT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
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#define SPI_DETECT_BEGIN_DATA_FRAME CFG0_TXURDT(0) /*!< underrun detected at start of data frame (no bit 1 protection) */
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#define SPI_DETECT_END_DATA_FRAME CFG0_TXURDT(1) /*!< underrun detected at end of last data frame */
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#define SPI_DETECT_BEGIN_ACTIVE_NSS CFG0_TXURDT(2) /*!< underrun detected at start of NSS signal */
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/* SPI CRC size */
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#define CFG0_CRCSZ(regval) (BITS(16,20) & ((uint32_t)(regval) << 16))
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#define SPI_CRCSIZE_4BIT CFG0_CRCSZ(3) /*!< SPI crc size is 4-bit */
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#define SPI_CRCSIZE_5BIT CFG0_CRCSZ(4) /*!< SPI crc size is 5-bit */
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#define SPI_CRCSIZE_6BIT CFG0_CRCSZ(5) /*!< SPI crc size is 6-bit */
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#define SPI_CRCSIZE_7BIT CFG0_CRCSZ(6) /*!< SPI crc size is 7-bit */
|
||||
#define SPI_CRCSIZE_8BIT CFG0_CRCSZ(7) /*!< SPI crc size is 8-bit */
|
||||
#define SPI_CRCSIZE_9BIT CFG0_CRCSZ(8) /*!< SPI crc size is 9-bit */
|
||||
#define SPI_CRCSIZE_10BIT CFG0_CRCSZ(9) /*!< SPI crc size is 10-bit */
|
||||
#define SPI_CRCSIZE_11BIT CFG0_CRCSZ(10) /*!< SPI crc size is 11-bit */
|
||||
#define SPI_CRCSIZE_12BIT CFG0_CRCSZ(11) /*!< SPI crc size is 12-bit */
|
||||
#define SPI_CRCSIZE_13BIT CFG0_CRCSZ(12) /*!< SPI crc size is 13-bit */
|
||||
#define SPI_CRCSIZE_14BIT CFG0_CRCSZ(13) /*!< SPI crc size is 14-bit */
|
||||
#define SPI_CRCSIZE_15BIT CFG0_CRCSZ(14) /*!< SPI crc size is 15-bit */
|
||||
#define SPI_CRCSIZE_16BIT CFG0_CRCSZ(15) /*!< SPI crc size is 16-bit */
|
||||
#define SPI_CRCSIZE_17BIT CFG0_CRCSZ(16) /*!< SPI crc size is 17-bit */
|
||||
#define SPI_CRCSIZE_18BIT CFG0_CRCSZ(17) /*!< SPI crc size is 18-bit */
|
||||
#define SPI_CRCSIZE_19BIT CFG0_CRCSZ(18) /*!< SPI crc size is 19-bit */
|
||||
#define SPI_CRCSIZE_20BIT CFG0_CRCSZ(19) /*!< SPI crc size is 20-bit */
|
||||
#define SPI_CRCSIZE_21BIT CFG0_CRCSZ(20) /*!< SPI crc size is 21-bit */
|
||||
#define SPI_CRCSIZE_22BIT CFG0_CRCSZ(21) /*!< SPI crc size is 22-bit */
|
||||
#define SPI_CRCSIZE_23BIT CFG0_CRCSZ(22) /*!< SPI crc size is 23-bit */
|
||||
#define SPI_CRCSIZE_24BIT CFG0_CRCSZ(23) /*!< SPI crc size is 24-bit */
|
||||
#define SPI_CRCSIZE_25BIT CFG0_CRCSZ(24) /*!< SPI crc size is 25-bit */
|
||||
#define SPI_CRCSIZE_26BIT CFG0_CRCSZ(25) /*!< SPI crc size is 26-bit */
|
||||
#define SPI_CRCSIZE_27BIT CFG0_CRCSZ(26) /*!< SPI crc size is 27-bit */
|
||||
#define SPI_CRCSIZE_28BIT CFG0_CRCSZ(27) /*!< SPI crc size is 28-bit */
|
||||
#define SPI_CRCSIZE_29BIT CFG0_CRCSZ(28) /*!< SPI crc size is 29-bit */
|
||||
#define SPI_CRCSIZE_30BIT CFG0_CRCSZ(29) /*!< SPI crc size is 30-bit */
|
||||
#define SPI_CRCSIZE_31BIT CFG0_CRCSZ(30) /*!< SPI crc size is 31-bit */
|
||||
#define SPI_CRCSIZE_32BIT CFG0_CRCSZ(31) /*!< SPI crc size is 32-bit */
|
||||
|
||||
/* SPI clock prescale factor */
|
||||
#define CFG0_PSC(regval) (BITS(28,30) & ((uint32_t)(regval) << 28))
|
||||
#define SPI_PSC_2 CFG0_PSC(0) /*!< SPI clock prescale factor is 2 */
|
||||
#define SPI_PSC_4 CFG0_PSC(1) /*!< SPI clock prescale factor is 4 */
|
||||
#define SPI_PSC_8 CFG0_PSC(2) /*!< SPI clock prescale factor is 8 */
|
||||
#define SPI_PSC_16 CFG0_PSC(3) /*!< SPI clock prescale factor is 16 */
|
||||
#define SPI_PSC_32 CFG0_PSC(4) /*!< SPI clock prescale factor is 32 */
|
||||
#define SPI_PSC_64 CFG0_PSC(5) /*!< SPI clock prescale factor is 64 */
|
||||
#define SPI_PSC_128 CFG0_PSC(6) /*!< SPI clock prescale factor is 128 */
|
||||
#define SPI_PSC_256 CFG0_PSC(7) /*!< SPI clock prescale factor is 256 */
|
||||
|
||||
/* SPI NSS idleness delay */
|
||||
#define CFG1_MSSD(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
|
||||
#define SPI_NSS_IDLENESS_00CYCLE CFG1_MSSD(0) /*!< no delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_01CYCLE CFG1_MSSD(1) /*!< 1 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_02CYCLE CFG1_MSSD(2) /*!< 2 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_03CYCLE CFG1_MSSD(3) /*!< 3 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_04CYCLE CFG1_MSSD(4) /*!< 4 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_05CYCLE CFG1_MSSD(5) /*!< 5 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_06CYCLE CFG1_MSSD(6) /*!< 6 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_07CYCLE CFG1_MSSD(7) /*!< 7 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_08CYCLE CFG1_MSSD(8) /*!< 8 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_09CYCLE CFG1_MSSD(9) /*!< 9 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_10CYCLE CFG1_MSSD(10) /*!< 10 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_11CYCLE CFG1_MSSD(11) /*!< 11 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_12CYCLE CFG1_MSSD(12) /*!< 12 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_13CYCLE CFG1_MSSD(13) /*!< 13 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_14CYCLE CFG1_MSSD(14) /*!< 14 clock cycle delay between active edge of NSS and transmittion */
|
||||
#define SPI_NSS_IDLENESS_15CYCLE CFG1_MSSD(15) /*!< 15 clock cycle delay between active edge of NSS and transmittion */
|
||||
|
||||
/* SPI master data frame delay */
|
||||
#define CFG1_MDFD(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
|
||||
#define SPI_DATA_IDLENESS_00CYCLE CFG1_MDFD(0) /*!< no delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_01CYCLE CFG1_MDFD(1) /*!< 1 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_02CYCLE CFG1_MDFD(2) /*!< 2 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_03CYCLE CFG1_MDFD(3) /*!< 3 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_04CYCLE CFG1_MDFD(4) /*!< 4 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_05CYCLE CFG1_MDFD(5) /*!< 5 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_06CYCLE CFG1_MDFD(6) /*!< 6 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_07CYCLE CFG1_MDFD(7) /*!< 7 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_08CYCLE CFG1_MDFD(8) /*!< 8 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_09CYCLE CFG1_MDFD(9) /*!< 9 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_10CYCLE CFG1_MDFD(10) /*!< 10 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_11CYCLE CFG1_MDFD(11) /*!< 11 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_12CYCLE CFG1_MDFD(12) /*!< 12 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_13CYCLE CFG1_MDFD(13) /*!< 13 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_14CYCLE CFG1_MDFD(14) /*!< 14 clock cycle delay between data frames in SPI master mode */
|
||||
#define SPI_DATA_IDLENESS_15CYCLE CFG1_MDFD(15) /*!< 15 clock cycle delay between data frames in SPI master mode */
|
||||
|
||||
/* SPI IO swap */
|
||||
#define SPI_IO_SWAP SPI_CFG1_SWPMIO /*!< SPI MOSI and MISO swap */
|
||||
#define SPI_IO_NORMAL (~SPI_CFG1_SWPMIO) /*!< SPI MOSI and MISO no swap */
|
||||
|
||||
/* SPI bidirectional transfer direction */
|
||||
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CFG1_BDOEN /*!< SPI work in transmit-only mode */
|
||||
#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CFG1_BDOEN) /*!< SPI work in receive-only mode */
|
||||
|
||||
/* SPI transmit type */
|
||||
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
|
||||
#define SPI_TRANSMODE_RECEIVEONLY SPI_CFG1_RO /*!< SPI only receive data */
|
||||
#define SPI_TRANSMODE_BDRECEIVE SPI_CFG1_BDEN /*!< bidirectional receive data */
|
||||
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CFG1_BDEN | SPI_CFG1_BDOEN) /*!< bidirectional transmit data*/
|
||||
|
||||
/* SPI mode definitions */
|
||||
#define SPI_MASTER SPI_CFG1_MSTMOD /*!< SPI as master */
|
||||
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
|
||||
|
||||
/* SPI transmit way */
|
||||
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
|
||||
#define SPI_ENDIAN_LSB SPI_CFG1_LF /*!< SPI transmit way is little endian: transmit LSB first */
|
||||
|
||||
/* SPI clock phase and polarity */
|
||||
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
|
||||
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CFG1_CKPL /*!< SPI clock polarity is high level and phase is first edge */
|
||||
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CFG1_CKPH /*!< SPI clock polarity is low level and phase is second edge */
|
||||
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CFG1_CKPL | SPI_CFG1_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
|
||||
|
||||
/* SPI NSS control mode */
|
||||
#define SPI_NSS_SOFT SPI_CFG1_NSSIM /*!< SPI NSS control by sofrware */
|
||||
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */
|
||||
|
||||
/* SPI NSS polarity */
|
||||
#define SPI_NSS_POLARITY_HIGH SPI_CFG1_NSSIOPL /*!< SPI NSS high level is active */
|
||||
#define SPI_NSS_POLARITY_LOW ((uint32_t)0x00000000U) /*!< SPI NSS low level is active */
|
||||
|
||||
/* SPI NSS output control */
|
||||
#define SPI_NSS_INVALID_PULSE SPI_CFG1_NSSCTL /*!< SPI data frames are interleaved with NSS invalid pulses */
|
||||
#define SPI_NSS_HOLD_UNTIL_TRANS_END ((uint32_t)0x00000000U) /*!< SPI NSS remains active level until data transfer complete */
|
||||
|
||||
/* SPI af gpio control */
|
||||
#define SPI_GPIO_CONTROL SPI_CFG1_AFCTL /*!< SPI always control all associated GPIO */
|
||||
#define SPI_GPIO_FREE ((uint32_t)0x00000000U) /*!< SPI do not control GPIO when disabled */
|
||||
|
||||
/* SPI RxFIFO packing level */
|
||||
#define STAT_RPLVL(regval) (BITS(13,14) & ((uint32_t)(regval) << 13))
|
||||
#define SPI_RX_FIFO_0PACKET STAT_RPLVL(0) /*!< no frame or 4 frames stored in RxFIFO */
|
||||
#define SPI_RX_FIFO_1PACKET STAT_RPLVL(1) /*!< 1 frame stored in RxFIFO */
|
||||
#define SPI_RX_FIFO_2PACKET STAT_RPLVL(2) /*!< 2 frames stored in RxFIFO */
|
||||
#define SPI_RX_FIFO_3PACKET STAT_RPLVL(3) /*!< 3 frames stored in RxFIFO */
|
||||
|
||||
/* I2S audio sample rate */
|
||||
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
|
||||
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
|
||||
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
|
||||
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
|
||||
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
|
||||
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
|
||||
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
|
||||
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
|
||||
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
|
||||
|
||||
/* I2S frame format */
|
||||
#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
|
||||
|
||||
/* I2S master clock output */
|
||||
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
|
||||
#define I2S_MCKOUT_ENABLE SPI_I2SCTL_MCKOEN /*!< I2S master clock output enable */
|
||||
|
||||
/* I2S operation mode */
|
||||
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
|
||||
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
|
||||
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
|
||||
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
|
||||
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
|
||||
|
||||
/* I2S standard */
|
||||
#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define I2S_STD_PHILIPS I2SCTL_I2SSTD(0) /*!< I2S philips standard */
|
||||
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
|
||||
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
|
||||
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
|
||||
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
|
||||
|
||||
/* I2S clock polarity */
|
||||
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
|
||||
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
|
||||
|
||||
/* SPI DMA constants definitions */
|
||||
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
|
||||
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
|
||||
|
||||
/* SPI CRC constants definitions */
|
||||
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
|
||||
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
|
||||
|
||||
/* SPI/I2S interrupt enable/disable constants definitions */
|
||||
#define SPI_I2S_INT_RP ((uint8_t)0x00U) /*!< RP interrupt */
|
||||
#define SPI_I2S_INT_TP ((uint8_t)0x01U) /*!< TP interrupt */
|
||||
#define SPI_I2S_INT_DP ((uint8_t)0x02U) /*!< DP interrupt */
|
||||
#define SPI_I2S_INT_ESTC ((uint8_t)0x03U) /*!< end of transfer or suspend or TXFIFO clear interrupt */
|
||||
#define SPI_I2S_INT_TXF ((uint8_t)0x04U) /*!< transmission filled interrupt */
|
||||
#define SPI_I2S_INT_TXURE ((uint8_t)0x05U) /*!< underrun error interrupt */
|
||||
#define SPI_I2S_INT_RXORE ((uint8_t)0x06U) /*!< overrun error interrupt */
|
||||
#define SPI_I2S_INT_CRCER ((uint8_t)0x07U) /*!< CRC error interrupt */
|
||||
#define SPI_I2S_INT_FE ((uint8_t)0x08U) /*!< TI frame error interrupt */
|
||||
#define SPI_I2S_INT_CONFE ((uint8_t)0x09U) /*!< mode error interrupt */
|
||||
#define SPI_I2S_INT_TXSERF ((uint8_t)0x0AU) /*!< TXSER reload interrupt */
|
||||
|
||||
/* SPI/I2S interrupt flag constants definitions */
|
||||
#define SPI_I2S_INT_FLAG_RP ((uint8_t)0x00U) /*!< RP interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_TP ((uint8_t)0x01U) /*!< TP interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_DP ((uint8_t)0x02U) /*!< DP interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_ET ((uint8_t)0x03U) /*!< end of transfer or receive interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_TXF ((uint8_t)0x04U) /*!< transmission filled interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x06U) /*!< overrun error interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_CRCERR ((uint8_t)0x07U) /*!< CRC error interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x08U) /*!< TI frame error interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_CONFERR ((uint8_t)0x09U) /*!< mode error interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_TXSERF ((uint8_t)0x0AU) /*!< TXSER reload interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_SPD ((uint8_t)0x0BU) /*!< suspend interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_TC ((uint8_t)0x0CU) /*!< TXFIFO clear interrupt flag */
|
||||
|
||||
/* SPI/I2S flag definitions */
|
||||
#define SPI_FLAG_RP SPI_STAT_RP /*!< RP flag */
|
||||
#define SPI_FLAG_TP SPI_STAT_TP /*!< TP flag */
|
||||
#define SPI_FLAG_DP SPI_STAT_DP /*!< DP flag */
|
||||
#define SPI_FLAG_ET SPI_STAT_ET /*!< end of transfer or receive flag */
|
||||
#define SPI_FLAG_TXF SPI_STAT_TXF /*!< transmission filled flag */
|
||||
#define SPI_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
|
||||
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
|
||||
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
|
||||
#define SPI_FLAG_FERR SPI_STAT_FERR /*!< TI frame error flag */
|
||||
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode error flag */
|
||||
#define SPI_FLAG_TXSERF SPI_STAT_TXSERF /*!< TXSER reload flag */
|
||||
#define SPI_FLAG_SPD SPI_STAT_SPD /*!< suspend flag */
|
||||
#define SPI_FLAG_TC SPI_STAT_TC /*!< TXFIFO clear flag */
|
||||
#define SPI_FLAG_RPLVL SPI_STAT_RPLVL /*!< RxFIFO packing level flag */
|
||||
#define SPI_FLAG_RWNE SPI_STAT_RWNE /*!< the word of RXFIFO is not empty flag */
|
||||
#define SPI_FLAG_CTXSIZE SPI_STAT_CTXSIZE /*!< the number of data frames remaining in the TXSIZE session flag */
|
||||
|
||||
#define I2S_FLAG_RP SPI_STAT_RP /*!< RP flag */
|
||||
#define I2S_FLAG_TP SPI_STAT_TP /*!< TP flag */
|
||||
#define I2S_FLAG_DP SPI_STAT_DP /*!< DP flag */
|
||||
#define I2S_FLAG_ET SPI_STAT_ET /*!< end of transfer or suspend or TXFIFO clear flag */
|
||||
#define I2S_FLAG_TXF SPI_STAT_TXF /*!< transmission filled flag */
|
||||
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
|
||||
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset SPI and I2S */
|
||||
void spi_i2s_deinit(uint32_t spi_periph);
|
||||
/* initialize the parameters of SPI struct with the default values */
|
||||
void spi_struct_para_init(spi_parameter_struct* spi_struct);
|
||||
/* initialize SPI parameter */
|
||||
void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct);
|
||||
/* enable SPI */
|
||||
void spi_enable(uint32_t spi_periph);
|
||||
/* disable SPI */
|
||||
void spi_disable(uint32_t spi_periph);
|
||||
|
||||
/* initialize I2S parameter */
|
||||
void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl);
|
||||
/* configure I2S prescaler */
|
||||
void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout);
|
||||
/* enable I2S */
|
||||
void i2s_enable(uint32_t spi_periph);
|
||||
/* disable I2S */
|
||||
void i2s_disable(uint32_t spi_periph);
|
||||
|
||||
/* IO swap functions */
|
||||
/* SPI MOSI and MISO pin swap */
|
||||
void spi_io_config(uint32_t spi_periph, uint32_t io_cfg);
|
||||
|
||||
/* SPI delay config functions */
|
||||
/* set delay between active edge of NSS and start transfer or receive data in SPI master mode */
|
||||
void spi_nss_idleness_delay_set(uint32_t spi_periph, uint32_t delay_cycle);
|
||||
/* set SPI master data frame delay */
|
||||
void spi_data_frame_delay_set(uint32_t spi_periph, uint32_t delay_cycle);
|
||||
/* set SPI master mode rx clock delay */
|
||||
void spi_master_receive_clock_delay_set(uint32_t spi_periph, uint32_t delay_unit);
|
||||
/* set SPI slave mode rx clock delay */
|
||||
void spi_slave_receive_clock_delay_set(uint32_t spi_periph, uint32_t delay_unit);
|
||||
/* clear SPI master mode rx clock delay */
|
||||
void spi_master_receive_clock_delay_clear(uint32_t spi_periph);
|
||||
/* clear SPI slave mode rx clock delay */
|
||||
void spi_slave_receive_clock_delay_clear(uint32_t spi_periph);
|
||||
|
||||
/* NSS functions */
|
||||
/* NSS output control */
|
||||
void spi_nss_output_control(uint32_t spi_periph, uint32_t nss_ctl);
|
||||
/* set SPI NSS active polarity */
|
||||
void spi_nss_polarity_set(uint32_t spi_periph, uint32_t polarity);
|
||||
/* enable SPI NSS output */
|
||||
void spi_nss_output_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS output */
|
||||
void spi_nss_output_disable(uint32_t spi_periph);
|
||||
/* SPI NSS pin high level in software mode */
|
||||
void spi_nss_internal_high(uint32_t spi_periph);
|
||||
/* SPI NSS pin low level in software mode */
|
||||
void spi_nss_internal_low(uint32_t spi_periph);
|
||||
|
||||
/* SPI DMA functions */
|
||||
/* enable SPI DMA */
|
||||
void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma);
|
||||
/* disable SPI DMA */
|
||||
void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma);
|
||||
|
||||
/* SPI/I2S transfer configure functions */
|
||||
/* configure SPI/I2S data frame size */
|
||||
void spi_i2s_data_frame_size_config(uint32_t spi_periph, uint32_t frame_size);
|
||||
/* SPI/I2S transmit data */
|
||||
void spi_i2s_data_transmit(uint32_t spi_periph, uint32_t data);
|
||||
/* SPI/I2S receive data */
|
||||
uint32_t spi_i2s_data_receive(uint32_t spi_periph);
|
||||
/* configure SPI bidirectional transfer direction */
|
||||
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
|
||||
/* SPI/I2S master start transfer */
|
||||
void spi_master_transfer_start(uint32_t spi_periph, uint32_t transfer_start);
|
||||
/* configure SPI current data number */
|
||||
void spi_current_data_num_config(uint32_t spi_periph, uint32_t current_num);
|
||||
/* configure SPI reload data number */
|
||||
void spi_reload_data_num_config(uint32_t spi_periph, uint32_t reload_num);
|
||||
|
||||
/* SPI CRC functions */
|
||||
/* set SPI CRC polynomial */
|
||||
void spi_crc_polynomial_set(uint32_t spi_periph, uint32_t crc_poly);
|
||||
/* get SPI CRC polynomial */
|
||||
uint32_t spi_crc_polynomial_get(uint32_t spi_periph);
|
||||
/* configure SPI CRC length */
|
||||
void spi_crc_length_config(uint32_t spi_periph, uint32_t crc_size);
|
||||
/* turn on SPI CRC function */
|
||||
void spi_crc_on(uint32_t spi_periph);
|
||||
/* turn off SPI CRC function */
|
||||
void spi_crc_off(uint32_t spi_periph);
|
||||
/* get SPI CRC send value or receive value */
|
||||
uint32_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
|
||||
/* enable SPI CRC full size(33 bit or 17 bit) polynomial */
|
||||
void spi_crc_full_size_enable(uint32_t spi_periph);
|
||||
/* disable SPI CRC full size(33 bit or 17 bit) polynomial */
|
||||
void spi_crc_full_size_disable(uint32_t spi_periph);
|
||||
/* configure SPI TCRC init pattern */
|
||||
void spi_tcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern);
|
||||
/* configure SPI RCRC init pattern */
|
||||
void spi_rcrc_init_pattern(uint32_t spi_periph, uint32_t init_pattern);
|
||||
|
||||
/* SPI TI mode functions */
|
||||
/* enable SPI TI mode */
|
||||
void spi_ti_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI TI mode */
|
||||
void spi_ti_mode_disable(uint32_t spi_periph);
|
||||
|
||||
/* quad wire SPI functions */
|
||||
/* enable quad wire SPI */
|
||||
void spi_quad_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI */
|
||||
void spi_quad_disable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI write */
|
||||
void spi_quad_write_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI read */
|
||||
void spi_quad_read_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void spi_quad_io23_output_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void spi_quad_io23_output_disable(uint32_t spi_periph);
|
||||
|
||||
/* SPI underrun functions */
|
||||
/* slave transmitter underrun detected operation */
|
||||
void spi_underrun_operation(uint32_t spi_periph, uint32_t ur_ope);
|
||||
/* configure slave transmitter underrun detected */
|
||||
void spi_underrun_config(uint32_t spi_periph, uint32_t ur_cfg);
|
||||
/* configure underrun data at slave mode */
|
||||
void spi_underrun_data_config(uint32_t spi_periph, uint32_t udata);
|
||||
|
||||
/* SPI suspend functions */
|
||||
/* configure SPI suspend in receive mode */
|
||||
void spi_suspend_mode_config(uint32_t spi_periph, uint32_t sus_mode);
|
||||
/* SPI master mode suspend request */
|
||||
void spi_suspend_request(uint32_t spi_periph);
|
||||
|
||||
/* SPI Related IOS AF functions */
|
||||
/* enable SPI related IOs AF */
|
||||
void spi_related_ios_af_enable(uint32_t spi_periph);
|
||||
/* disable SPI related IOs AF */
|
||||
void spi_related_ios_af_disable(uint32_t spi_periph);
|
||||
/* SPI af gpio control */
|
||||
void spi_af_gpio_control(uint32_t spi_periph, uint32_t ctl);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* enable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* disable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* get SPI and I2S interrupt flag status */
|
||||
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* get SPI and I2S flag status */
|
||||
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
|
||||
/* clear SPI and I2S flag status */
|
||||
void spi_i2s_flag_clear(uint32_t spi_periph, uint32_t flag);
|
||||
/* get SPI and I2S RXFIFO packing level */
|
||||
uint32_t spi_i2s_rxfifo_plevel_get(uint32_t spi_periph);
|
||||
/* get SPI and I2S remaining data frames number in the TXSIZE session */
|
||||
uint32_t spi_i2s_remain_data_num_get(uint32_t spi_periph);
|
||||
|
||||
/* SPI FIFO configure */
|
||||
/* set SPI FIFO threshold level */
|
||||
void spi_fifo_threshold_level_set(uint32_t spi_periph, uint32_t fifo_thl);
|
||||
/* enable SPI word access */
|
||||
void spi_word_access_enable(uint32_t spi_periph);
|
||||
/* disable SPI word access */
|
||||
void spi_word_access_disable(uint32_t spi_periph);
|
||||
/* enable SPI byte access */
|
||||
void spi_byte_access_enable(uint32_t spi_periph);
|
||||
/* disable SPI byte access */
|
||||
void spi_byte_access_disable(uint32_t spi_periph);
|
||||
|
||||
#endif /* GD32H7XX_SPI_H */
|
||||
Reference in New Issue
Block a user