323 lines
19 KiB
C
323 lines
19 KiB
C
/*!
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\file gd32h7xx_cau.h
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\brief definitions for the CAU
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\version 2025-01-24, V1.4.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H7XX_CAU_H
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#define GD32H7XX_CAU_H
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#include "gd32h7xx.h"
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/* CAU definitions */
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#define CAU CAU_BASE /*!< CAU base address */
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/* registers definitions */
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#define CAU_CTL REG32(CAU + 0x00000000U) /*!< control register */
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#define CAU_STAT0 REG32(CAU + 0x00000004U) /*!< status register 0 */
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#define CAU_DI REG32(CAU + 0x00000008U) /*!< data input register */
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#define CAU_DO REG32(CAU + 0x0000000CU) /*!< data output register */
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#define CAU_DMAEN REG32(CAU + 0x00000010U) /*!< DMA enable register */
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#define CAU_INTEN REG32(CAU + 0x00000014U) /*!< interrupt enable register */
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#define CAU_STAT1 REG32(CAU + 0x00000018U) /*!< status register 1 */
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#define CAU_INTF REG32(CAU + 0x0000001CU) /*!< interrupt flag register */
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#define CAU_KEY0H REG32(CAU + 0x00000020U) /*!< key 0 high register */
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#define CAU_KEY0L REG32(CAU + 0x00000024U) /*!< key 0 low register */
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#define CAU_KEY1H REG32(CAU + 0x00000028U) /*!< key 1 high register */
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#define CAU_KEY1L REG32(CAU + 0x0000002CU) /*!< key 1 low register */
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#define CAU_KEY2H REG32(CAU + 0x00000030U) /*!< key 2 high register */
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#define CAU_KEY2L REG32(CAU + 0x00000034U) /*!< key 2 low register */
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#define CAU_KEY3H REG32(CAU + 0x00000038U) /*!< key 3 high register */
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#define CAU_KEY3L REG32(CAU + 0x0000003CU) /*!< key 3 low register */
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#define CAU_IV0H REG32(CAU + 0x00000040U) /*!< initial vector 0 high register */
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#define CAU_IV0L REG32(CAU + 0x00000044U) /*!< initial vector 0 low register */
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#define CAU_IV1H REG32(CAU + 0x00000048U) /*!< initial vector 1 high register */
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#define CAU_IV1L REG32(CAU + 0x0000004CU) /*!< initial vector 1 low register */
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#define CAU_GCMCCMCTXSx(x) REG32(CAU + 0x00000050U + (uint32_t)(4U * (x))) /*!< GCM or CCM mode context switch register, x = 0...7 */
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#define CAU_GCMCTXSx(x) REG32(CAU + 0x00000070U + (uint32_t)(4U * (x))) /*!< GCM mode context switch register, x = 0...7 */
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/* bits definitions */
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/* CAU_CTL */
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#define CAU_CTL_KEY_SEL BIT(0) /*!< key select */
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#define CAU_CTL_CAUDIR BIT(2) /*!< algorithm direction */
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#define CAU_CTL_ALGM (BITS(3,5) | BIT(19)) /*!< cryptographic algorithm mode */
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#define CAU_CTL_DATAM BITS(6,7) /*!< data swapping selection */
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#define CAU_CTL_KEYM BITS(8,9) /*!< key length selection when aes mode */
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#define CAU_CTL_FFLUSH BIT(14) /*!< FIFO flush */
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#define CAU_CTL_CAUEN BIT(15) /*!< cryptographic module enable */
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#define CAU_CTL_GCM_CCMPH BITS(16,17) /*!< GCM CCM phase */
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#define CAU_CTL_NBPILB BITS(20,23) /*!< number of bytes padding in last block */
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/* CAU_STAT0 */
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#define CAU_STAT0_IEM BIT(0) /*!< IN FIFO empty flag */
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#define CAU_STAT0_INF BIT(1) /*!< IN FIFO not full flag */
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#define CAU_STAT0_ONE BIT(2) /*!< OUT FIFO not empty flag */
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#define CAU_STAT0_OFU BIT(3) /*!< OUT FIFO full flag */
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#define CAU_STAT0_BUSY BIT(4) /*!< busy flag */
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/* CAU_DI */
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#define CAU_DI_DI BITS(0,31) /*!< data input */
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/* CAU_DO */
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#define CAU_DO_DO BITS(0,31) /*!< data output */
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/* CAU_DMAEN */
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#define CAU_DMAEN_DMAIEN BIT(0) /*!< IN FIFO DMA enable */
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#define CAU_DMAEN_DMAOEN BIT(1) /*!< OUT FIFO DMA enable */
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/* CAU_INTEN */
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#define CAU_INTEN_IINTEN BIT(0) /*!< IN FIFO interrupt enable */
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#define CAU_INTEN_OINTEN BIT(1) /*!< OUT FIFO interrupt enable */
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/* CAU_STAT1 */
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#define CAU_STAT1_ISTA BIT(0) /*!< flag set when there is less than 4 words in IN FIFO */
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#define CAU_STAT1_OSTA BIT(1) /*!< flag set when there is one or more word in OUT FIFO */
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/* CAU_INTF */
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#define CAU_INTF_IINTF BIT(0) /*!< IN FIFO interrupt flag */
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#define CAU_INTF_OINTF BIT(1) /*!< OUT FIFO interrupt flag */
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/* CAU_KEYxH x=0..3 */
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#define CAU_KEYXH_KEYXH BITS(0,31) /*!< the key for des, tdes, aes */
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/* CAU_KEYxL x=0..3 */
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#define CAU_KEYXL_KEYXL BITS(0,31) /*!< the key for des, tdes, aes */
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/* CAU_IVxH x=0..1 */
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#define CAU_IVXH_IVXH BITS(0,31) /*!< the initialization vector for des, tdes, aes */
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/* CAU_IVxL x=0..1 */
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#define CAU_IVXL_IVXL BITS(0,31) /*!< the initialization vector for des, tdes, aes */
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/* constants definitions */
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/* structure for keys initialization of the cau */
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typedef struct {
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uint32_t key_0_high; /*!< key 0 high */
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uint32_t key_0_low; /*!< key 0 low */
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uint32_t key_1_high; /*!< key 1 high */
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uint32_t key_1_low; /*!< key 1 low */
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uint32_t key_2_high; /*!< key 2 high */
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uint32_t key_2_low; /*!< key 2 low */
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uint32_t key_3_high; /*!< key 3 high */
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uint32_t key_3_low; /*!< key 3 low */
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} cau_key_parameter_struct;
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/* structure for vectors initialization of the cau */
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typedef struct {
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uint32_t iv_0_high; /*!< init vector 0 high */
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uint32_t iv_0_low; /*!< init vector 0 low */
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uint32_t iv_1_high; /*!< init vector 1 high */
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uint32_t iv_1_low; /*!< init vector 1 low */
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} cau_iv_parameter_struct;
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/* structure for cau context swapping */
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typedef struct {
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uint32_t ctl_config; /*!< current configuration */
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uint32_t iv_0_high; /*!< init vector 0 high */
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uint32_t iv_0_low; /*!< init vector 0 low */
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uint32_t iv_1_high; /*!< init vector 1 high */
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uint32_t iv_1_low; /*!< init vector 1 low */
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uint32_t key_0_high; /*!< key 0 high */
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uint32_t key_0_low; /*!< key 0 low */
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uint32_t key_1_high; /*!< key 1 high */
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uint32_t key_1_low; /*!< key 1 low */
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uint32_t key_2_high; /*!< key 2 high */
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uint32_t key_2_low; /*!< key 2 low */
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uint32_t key_3_high; /*!< key 3 high */
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uint32_t key_3_low; /*!< key 3 low */
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uint32_t gcmccmctxs[8]; /*!< GCM or CCM mode context switch */
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uint32_t gcmctxs[8]; /*!< GCM mode context switch */
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} cau_context_parameter_struct;
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/* structure for encrypt and decrypt parameters */
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typedef struct {
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uint32_t alg_dir; /*!< algorithm directory */
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uint8_t *key; /*!< key */
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uint32_t key_size; /*!< key size in bytes */
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uint8_t *iv; /*!< initialization vector */
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uint32_t iv_size; /*!< iv size in bytes */
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uint8_t *input; /*!< input data */
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uint32_t in_length; /*!< input data length in bytes */
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uint8_t *aad; /*!< additional authentication data */
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uint32_t aad_size; /*!< aad size */
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} cau_parameter_struct;
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/* cau_ctl register value */
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#define CAU_ENCRYPT ((uint32_t)0x00000000U) /*!< encrypt */
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#define CAU_DECRYPT CAU_CTL_CAUDIR /*!< decrypt */
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#define CTL_ALGM(regval) ((BITS(3,5) & ((uint32_t)(regval) << 3U)) | \
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(BIT(19) & ((uint32_t)(regval) << 16U))) /*!< write value to CAU_CTL_ALGM bit field */
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#define CAU_MODE_TDES_ECB CTL_ALGM(0) /*!< TDES-ECB (3DES Electronic codebook) */
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#define CAU_MODE_TDES_CBC CTL_ALGM(1) /*!< TDES-CBC (3DES Cipher block chaining) */
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#define CAU_MODE_DES_ECB CTL_ALGM(2) /*!< DES-ECB (simple DES Electronic codebook) */
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#define CAU_MODE_DES_CBC CTL_ALGM(3) /*!< DES-CBC (simple DES Cipher block chaining) */
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#define CAU_MODE_AES_ECB CTL_ALGM(4) /*!< AES-ECB (AES Electronic codebook) */
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#define CAU_MODE_AES_CBC CTL_ALGM(5) /*!< AES-CBC (AES Cipher block chaining) */
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#define CAU_MODE_AES_CTR CTL_ALGM(6) /*!< AES-CTR (AES counter mode) */
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#define CAU_MODE_AES_KEY CTL_ALGM(7) /*!< AES decryption key preparation mode */
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#define CAU_MODE_AES_GCM CTL_ALGM(8) /*!< AES-GCM (AES Galois/counter mode) */
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#define CAU_MODE_AES_CCM CTL_ALGM(9) /*!< AES-CCM (AES combined cipher machine mode) */
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#define CAU_MODE_AES_CFB CTL_ALGM(10) /*!< AES-CFB (cipher feedback mode) */
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#define CAU_MODE_AES_OFB CTL_ALGM(11) /*!< AES-OFB (output feedback mode) */
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#define CTL_DATAM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U)) /*!< write value to CAU_CTL_DATAM bit field */
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#define CAU_SWAPPING_32BIT CTL_DATAM(0) /*!< no swapping */
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#define CAU_SWAPPING_16BIT CTL_DATAM(1) /*!< half-word swapping */
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#define CAU_SWAPPING_8BIT CTL_DATAM(2) /*!< bytes swapping */
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#define CAU_SWAPPING_1BIT CTL_DATAM(3) /*!< bit swapping */
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#define CAU_KEY 0x00000000U /*!< use the key from CAU register */
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#define CAU_EFUSE_KEY 0x00000001U /*!< use the key from EFUSE */
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#define CTL_KEYM(regval) (BITS(8,9) & ((uint32_t)(regval) << 8U)) /*!< write value to CAU_CTL_KEYM bit field */
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#define CAU_KEYSIZE_128BIT CTL_KEYM(0) /*!< 128 bit key length */
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#define CAU_KEYSIZE_192BIT CTL_KEYM(1) /*!< 192 bit key length */
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#define CAU_KEYSIZE_256BIT CTL_KEYM(2) /*!< 256 bit key length */
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#define CTL_GCM_CCMPH(regval) (BITS(16,17) & ((uint32_t)(regval) << 16U)) /*!< write value to CAU_CTL_GCM_CCMPH bit field */
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#define CAU_PREPARE_PHASE CTL_GCM_CCMPH(0) /*!< prepare phase */
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#define CAU_AAD_PHASE CTL_GCM_CCMPH(1) /*!< AAD phase */
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#define CAU_ENCRYPT_DECRYPT_PHASE CTL_GCM_CCMPH(2) /*!< encryption/decryption phase */
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#define CAU_TAG_PHASE CTL_GCM_CCMPH(3) /*!< tag phase */
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#define CAU_PADDING_BYTES(regval) (BITS(20, 23) & ((uint32_t)(regval) << 20U))
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/* cau_stat0 register value */
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#define CAU_FLAG_INFIFO_EMPTY CAU_STAT0_IEM /*!< IN FIFO empty */
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#define CAU_FLAG_INFIFO_NO_FULL CAU_STAT0_INF /*!< IN FIFO is not full */
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#define CAU_FLAG_OUTFIFO_NO_EMPTY CAU_STAT0_ONE /*!< OUT FIFO not empty */
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#define CAU_FLAG_OUTFIFO_FULL CAU_STAT0_OFU /*!< OUT FIFO is full */
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#define CAU_FLAG_BUSY CAU_STAT0_BUSY /*!< the CAU core is busy */
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/* cau_dmaen register value */
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#define CAU_DMA_INFIFO CAU_DMAEN_DMAIEN /*!< DMA input enable */
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#define CAU_DMA_OUTFIFO CAU_DMAEN_DMAOEN /*!< DMA output enable */
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/* cau_inten register value */
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#define CAU_INT_INFIFO CAU_INTEN_IINTEN /*!< IN FIFO Interrupt */
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#define CAU_INT_OUTFIFO CAU_INTEN_OINTEN /*!< OUT FIFO Interrupt */
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/* cau_stat1 register value */
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#define CAU_FLAG_INFIFO (CAU_STAT1_ISTA | BIT(31)) /*!< IN FIFO flag status */
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#define CAU_FLAG_OUTFIFO (CAU_STAT1_OSTA | BIT(31)) /*!< OUT FIFO flag status */
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/* cau_intf register value */
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#define CAU_INT_FLAG_INFIFO CAU_INTF_IINTF /*!< IN FIFO interrupt status */
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#define CAU_INT_FLAG_OUTFIFO CAU_INTF_OINTF /*!< OUT FIFO interrupt status */
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/* function declarations */
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/* initialization functions */
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/* reset the CAU peripheral */
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void cau_deinit(void);
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/* initialize the CAU encrypt and decrypt parameter struct with the default values */
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void cau_struct_para_init(cau_parameter_struct *cau_parameter);
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/* initialize the key parameter struct with the default values */
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void cau_key_struct_para_init(cau_key_parameter_struct *key_initpara);
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/* initialize the vectors parameter struct with the default values */
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void cau_iv_struct_para_init(cau_iv_parameter_struct *iv_initpara);
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/* initialize the context parameter struct with the default values */
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void cau_context_struct_para_init(cau_context_parameter_struct *cau_context);
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/* configuration functions */
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/* enable the CAU peripheral */
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void cau_enable(void);
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/* disable the CAU peripheral */
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void cau_disable(void);
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/* enable the CAU DMA interface */
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void cau_dma_enable(uint32_t dma_req);
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/* disable the CAU DMA interface */
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void cau_dma_disable(uint32_t dma_req);
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/* initialize the CAU peripheral */
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void cau_init(uint32_t alg_dir, uint32_t algo_mode, uint32_t swapping);
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/* configure key selection */
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void cau_aes_key_select(uint32_t key_selection);
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/* configure key size if use AES algorithm */
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void cau_aes_keysize_config(uint32_t key_size);
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/* initialize the key parameters */
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void cau_key_init(cau_key_parameter_struct *key_initpara);
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/* initialize the vectors parameters */
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void cau_iv_init(cau_iv_parameter_struct *iv_initpara);
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/* configure phase */
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void cau_phase_config(uint32_t phase);
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/* flush the IN and OUT FIFOs */
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void cau_fifo_flush(void);
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/* return whether CAU peripheral is enabled or disabled */
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ControlStatus cau_enable_state_get(void);
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/* read and write functions */
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/* write data to the IN FIFO */
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void cau_data_write(uint32_t data);
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/* return the last data entered into the output FIFO */
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uint32_t cau_data_read(void);
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/* context switch functions */
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/* save context before context switching */
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void cau_context_save(cau_context_parameter_struct *cau_context, cau_key_parameter_struct *key_initpara);
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/* restore context after context switching */
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void cau_context_restore(cau_context_parameter_struct *cau_context);
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/* encrypt and decrypt functions */
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/* encrypt and decrypt using AES in ECB mode */
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ErrStatus cau_aes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output);
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/* encrypt and decrypt using AES in CBC mode */
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ErrStatus cau_aes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output);
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/* encrypt and decrypt using AES in CTR mode */
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ErrStatus cau_aes_ctr(cau_parameter_struct *cau_parameter, uint8_t *output);
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/* encrypt and decrypt using AES in CFB mode */
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ErrStatus cau_aes_cfb(cau_parameter_struct *cau_parameter, uint8_t *output);
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/* encrypt and decrypt using AES in OFB mode */
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ErrStatus cau_aes_ofb(cau_parameter_struct *cau_parameter, uint8_t *output);
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/* encrypt and decrypt using AES in GCM mode */
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ErrStatus cau_aes_gcm(cau_parameter_struct *cau_parameter, uint8_t *output, uint8_t *tag);
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/* encrypt and decrypt using AES in CCM mode */
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ErrStatus cau_aes_ccm(cau_parameter_struct *cau_parameter, uint8_t *output, uint8_t tag[], uint32_t tag_size, uint8_t aad_buf[]);
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/* encrypt and decrypt using TDES in ECB mode */
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ErrStatus cau_tdes_ecb(cau_parameter_struct *cau_parameter, uint8_t *output);
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/* encrypt and decrypt using TDES in CBC mode */
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ErrStatus cau_tdes_cbc(cau_parameter_struct *cau_parameter, uint8_t *output);
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/* encrypt and decrypt using DES in ECB mode */
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ErrStatus cau_des_ecb(cau_parameter_struct *cau_parameter, uint8_t *output);
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/* encrypt and decrypt using DES in CBC mode */
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ErrStatus cau_des_cbc(cau_parameter_struct *cau_parameter, uint8_t *output);
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/* interrupt & flag functions */
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/* get the CAU flag status */
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FlagStatus cau_flag_get(uint32_t flag);
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/* enable the CAU interrupts */
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void cau_interrupt_enable(uint32_t interrupt);
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/* disable the CAU interrupts */
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void cau_interrupt_disable(uint32_t interrupt);
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/* get the interrupt flag */
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FlagStatus cau_interrupt_flag_get(uint32_t int_flag);
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#endif /* GD32H7XX_CAU_H */
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