366 lines
32 KiB
C
366 lines
32 KiB
C
/*!
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\file gd32h7xx_hwsem.h
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\brief definitions for the HWSEM
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\version 2025-01-24, V1.4.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H7XX_HWSEM_H
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#define GD32H7XX_HWSEM_H
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#include "gd32h7xx.h"
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/* HWSEM definitions */
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#define HWSEM HWSEM_BASE /*!< HWSEM base address */
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/* registers definitions */
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#define HWSEM_CTL0 REG32(HWSEM + 0x00000000U) /*!< HWSEM control register 0 */
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#define HWSEM_CTL1 REG32(HWSEM + 0x00000004U) /*!< HWSEM control register 1 */
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#define HWSEM_CTL2 REG32(HWSEM + 0x00000008U) /*!< HWSEM control register 2 */
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#define HWSEM_CTL3 REG32(HWSEM + 0x0000000CU) /*!< HWSEM control register 3 */
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#define HWSEM_CTL4 REG32(HWSEM + 0x00000010U) /*!< HWSEM control register 4 */
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#define HWSEM_CTL5 REG32(HWSEM + 0x00000014U) /*!< HWSEM control register 5 */
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#define HWSEM_CTL6 REG32(HWSEM + 0x00000018U) /*!< HWSEM control register 6 */
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#define HWSEM_CTL7 REG32(HWSEM + 0x0000001CU) /*!< HWSEM control register 7 */
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#define HWSEM_CTL8 REG32(HWSEM + 0x00000020U) /*!< HWSEM control register 8 */
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#define HWSEM_CTL9 REG32(HWSEM + 0x00000024U) /*!< HWSEM control register 9 */
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#define HWSEM_CTL10 REG32(HWSEM + 0x00000028U) /*!< HWSEM control register 10 */
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#define HWSEM_CTL11 REG32(HWSEM + 0x0000002CU) /*!< HWSEM control register 11 */
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#define HWSEM_CTL12 REG32(HWSEM + 0x00000030U) /*!< HWSEM control register 12 */
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#define HWSEM_CTL13 REG32(HWSEM + 0x00000034U) /*!< HWSEM control register 13 */
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#define HWSEM_CTL14 REG32(HWSEM + 0x00000038U) /*!< HWSEM control register 14 */
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#define HWSEM_CTL15 REG32(HWSEM + 0x0000003CU) /*!< HWSEM control register 15 */
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#define HWSEM_CTL16 REG32(HWSEM + 0x00000040U) /*!< HWSEM control register 16 */
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#define HWSEM_CTL17 REG32(HWSEM + 0x00000044U) /*!< HWSEM control register 17 */
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#define HWSEM_CTL18 REG32(HWSEM + 0x00000048U) /*!< HWSEM control register 18 */
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#define HWSEM_CTL19 REG32(HWSEM + 0x0000004CU) /*!< HWSEM control register 19 */
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#define HWSEM_CTL20 REG32(HWSEM + 0x00000050U) /*!< HWSEM control register 20 */
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#define HWSEM_CTL21 REG32(HWSEM + 0x00000054U) /*!< HWSEM control register 21 */
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#define HWSEM_CTL22 REG32(HWSEM + 0x00000058U) /*!< HWSEM control register 22 */
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#define HWSEM_CTL23 REG32(HWSEM + 0x0000005CU) /*!< HWSEM control register 23 */
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#define HWSEM_CTL24 REG32(HWSEM + 0x00000060U) /*!< HWSEM control register 24 */
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#define HWSEM_CTL25 REG32(HWSEM + 0x00000064U) /*!< HWSEM control register 25 */
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#define HWSEM_CTL26 REG32(HWSEM + 0x00000068U) /*!< HWSEM control register 26 */
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#define HWSEM_CTL27 REG32(HWSEM + 0x0000006CU) /*!< HWSEM control register 27 */
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#define HWSEM_CTL28 REG32(HWSEM + 0x00000070U) /*!< HWSEM control register 28 */
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#define HWSEM_CTL29 REG32(HWSEM + 0x00000074U) /*!< HWSEM control register 29 */
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#define HWSEM_CTL30 REG32(HWSEM + 0x00000078U) /*!< HWSEM control register 30 */
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#define HWSEM_CTL31 REG32(HWSEM + 0x0000007CU) /*!< HWSEM control register 31 */
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#define HWSEM_RLK0 REG32(HWSEM + 0x00000080U) /*!< HWSEM read lock register 0 */
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#define HWSEM_RLK1 REG32(HWSEM + 0x00000084U) /*!< HWSEM read lock register 1 */
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#define HWSEM_RLK2 REG32(HWSEM + 0x00000088U) /*!< HWSEM read lock register 2 */
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#define HWSEM_RLK3 REG32(HWSEM + 0x0000008CU) /*!< HWSEM read lock register 3 */
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#define HWSEM_RLK4 REG32(HWSEM + 0x00000090U) /*!< HWSEM read lock register 4 */
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#define HWSEM_RLK5 REG32(HWSEM + 0x00000094U) /*!< HWSEM read lock register 5 */
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#define HWSEM_RLK6 REG32(HWSEM + 0x00000098U) /*!< HWSEM read lock register 6 */
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#define HWSEM_RLK7 REG32(HWSEM + 0x0000009CU) /*!< HWSEM read lock register 7 */
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#define HWSEM_RLK8 REG32(HWSEM + 0x000000A0U) /*!< HWSEM read lock register 8 */
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#define HWSEM_RLK9 REG32(HWSEM + 0x000000A4U) /*!< HWSEM read lock register 9 */
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#define HWSEM_RLK10 REG32(HWSEM + 0x000000A8U) /*!< HWSEM read lock register 10 */
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#define HWSEM_RLK11 REG32(HWSEM + 0x000000ACU) /*!< HWSEM read lock register 11 */
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#define HWSEM_RLK12 REG32(HWSEM + 0x000000B0U) /*!< HWSEM read lock register 12 */
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#define HWSEM_RLK13 REG32(HWSEM + 0x000000B4U) /*!< HWSEM read lock register 13 */
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#define HWSEM_RLK14 REG32(HWSEM + 0x000000B8U) /*!< HWSEM read lock register 14 */
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#define HWSEM_RLK15 REG32(HWSEM + 0x000000BCU) /*!< HWSEM read lock register 15 */
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#define HWSEM_RLK16 REG32(HWSEM + 0x000000C0U) /*!< HWSEM read lock register 16 */
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#define HWSEM_RLK17 REG32(HWSEM + 0x000000C4U) /*!< HWSEM read lock register 17 */
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#define HWSEM_RLK18 REG32(HWSEM + 0x000000C8U) /*!< HWSEM read lock register 18 */
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#define HWSEM_RLK19 REG32(HWSEM + 0x000000CCU) /*!< HWSEM read lock register 19 */
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#define HWSEM_RLK20 REG32(HWSEM + 0x000000D0U) /*!< HWSEM read lock register 20 */
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#define HWSEM_RLK21 REG32(HWSEM + 0x000000D4U) /*!< HWSEM read lock register 21 */
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#define HWSEM_RLK22 REG32(HWSEM + 0x000000D8U) /*!< HWSEM read lock register 22 */
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#define HWSEM_RLK23 REG32(HWSEM + 0x000000DCU) /*!< HWSEM read lock register 23 */
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#define HWSEM_RLK24 REG32(HWSEM + 0x000000E0U) /*!< HWSEM read lock register 24 */
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#define HWSEM_RLK25 REG32(HWSEM + 0x000000E4U) /*!< HWSEM read lock register 25 */
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#define HWSEM_RLK26 REG32(HWSEM + 0x000000E8U) /*!< HWSEM read lock register 26 */
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#define HWSEM_RLK27 REG32(HWSEM + 0x000000ECU) /*!< HWSEM read lock register 27 */
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#define HWSEM_RLK28 REG32(HWSEM + 0x000000F0U) /*!< HWSEM read lock register 28 */
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#define HWSEM_RLK29 REG32(HWSEM + 0x000000F4U) /*!< HWSEM read lock register 29 */
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#define HWSEM_RLK30 REG32(HWSEM + 0x000000F8U) /*!< HWSEM read lock register 30 */
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#define HWSEM_RLK31 REG32(HWSEM + 0x000000FCU) /*!< HWSEM read lock register 31 */
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#define HWSEM_INTEN REG32(HWSEM + 0x00000100U) /*!< HWSEM interrupt enable register */
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#define HWSEM_INTC REG32(HWSEM + 0x00000104U) /*!< HWSEM interrupt flag clear register */
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#define HWSEM_STAT REG32(HWSEM + 0x00000108U) /*!< HWSEM status register */
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#define HWSEM_INTF REG32(HWSEM + 0x0000010CU) /*!< HWSEM interrupt flag register */
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#define HWSEM_UNLK REG32(HWSEM + 0x00000140U) /*!< HWSEM unlock register */
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#define HWSEM_KEY REG32(HWSEM + 0x00000144U) /*!< HWSEM key register */
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/* bits definitions */
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/* HWSEM_CTLx, x=0..31 */
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#define HWSEM_CTL_PID BITS(0,7) /*!< HWSEM process ID */
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#define HWSEM_CTL_MID BITS(8,11) /*!< HWSEM master ID */
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#define HWSEM_CTL_LK BIT(31) /*!< HWSEM lock */
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/* HWSEM_RLKx, x=0..31 */
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#define HWSEM_RLK_PID BITS(0,7) /*!< HWSEM read lock register process ID */
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#define HWSEM_RLK_MID BITS(8,11) /*!< HWSEM read lock register master ID */
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#define HWSEM_RLK_LK BIT(31) /*!< HWSEM read lock register lock */
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/* HWSEM_INTEN */
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#define HWSEM_INTEN_SIE0 BIT(0) /*!< enable HWSEM interrupt for semaphore 0 */
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#define HWSEM_INTEN_SIE1 BIT(1) /*!< enable HWSEM interrupt for semaphore 1 */
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#define HWSEM_INTEN_SIE2 BIT(2) /*!< enable HWSEM interrupt for semaphore 2 */
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#define HWSEM_INTEN_SIE3 BIT(3) /*!< enable HWSEM interrupt for semaphore 3 */
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#define HWSEM_INTEN_SIE4 BIT(4) /*!< enable HWSEM interrupt for semaphore 4 */
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#define HWSEM_INTEN_SIE5 BIT(5) /*!< enable HWSEM interrupt for semaphore 5 */
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#define HWSEM_INTEN_SIE6 BIT(6) /*!< enable HWSEM interrupt for semaphore 6 */
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#define HWSEM_INTEN_SIE7 BIT(7) /*!< enable HWSEM interrupt for semaphore 7 */
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#define HWSEM_INTEN_SIE8 BIT(8) /*!< enable HWSEM interrupt for semaphore 8 */
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#define HWSEM_INTEN_SIE9 BIT(9) /*!< enable HWSEM interrupt for semaphore 9 */
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#define HWSEM_INTEN_SIE10 BIT(10) /*!< enable HWSEM interrupt for semaphore 10 */
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#define HWSEM_INTEN_SIE11 BIT(11) /*!< enable HWSEM interrupt for semaphore 11 */
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#define HWSEM_INTEN_SIE12 BIT(12) /*!< enable HWSEM interrupt for semaphore 12 */
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#define HWSEM_INTEN_SIE13 BIT(13) /*!< enable HWSEM interrupt for semaphore 13 */
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#define HWSEM_INTEN_SIE14 BIT(14) /*!< enable HWSEM interrupt for semaphore 14 */
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#define HWSEM_INTEN_SIE15 BIT(15) /*!< enable HWSEM interrupt for semaphore 15 */
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#define HWSEM_INTEN_SIE16 BIT(16) /*!< enable HWSEM interrupt for semaphore 16 */
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#define HWSEM_INTEN_SIE17 BIT(17) /*!< enable HWSEM interrupt for semaphore 17 */
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#define HWSEM_INTEN_SIE18 BIT(18) /*!< enable HWSEM interrupt for semaphore 18 */
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#define HWSEM_INTEN_SIE19 BIT(19) /*!< enable HWSEM interrupt for semaphore 19 */
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#define HWSEM_INTEN_SIE20 BIT(20) /*!< enable HWSEM interrupt for semaphore 20 */
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#define HWSEM_INTEN_SIE21 BIT(21) /*!< enable HWSEM interrupt for semaphore 21 */
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#define HWSEM_INTEN_SIE22 BIT(22) /*!< enable HWSEM interrupt for semaphore 22 */
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#define HWSEM_INTEN_SIE23 BIT(23) /*!< enable HWSEM interrupt for semaphore 23 */
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#define HWSEM_INTEN_SIE24 BIT(24) /*!< enable HWSEM interrupt for semaphore 24 */
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#define HWSEM_INTEN_SIE25 BIT(25) /*!< enable HWSEM interrupt for semaphore 25 */
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#define HWSEM_INTEN_SIE26 BIT(26) /*!< enable HWSEM interrupt for semaphore 26 */
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#define HWSEM_INTEN_SIE27 BIT(27) /*!< enable HWSEM interrupt for semaphore 27 */
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#define HWSEM_INTEN_SIE28 BIT(28) /*!< enable HWSEM interrupt for semaphore 28 */
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#define HWSEM_INTEN_SIE29 BIT(29) /*!< enable HWSEM interrupt for semaphore 29 */
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#define HWSEM_INTEN_SIE30 BIT(30) /*!< enable HWSEM interrupt for semaphore 30 */
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#define HWSEM_INTEN_SIE31 BIT(31) /*!< enable HWSEM interrupt for semaphore 31 */
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/* HWSEM_INTC */
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#define HWSEM_INTC_SIFC0 BIT(0) /*!< clear semaphore 0 flag and interrupt flag */
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#define HWSEM_INTC_SIFC1 BIT(1) /*!< clear semaphore 1 flag and interrupt flag */
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#define HWSEM_INTC_SIFC2 BIT(2) /*!< clear semaphore 2 flag and interrupt flag */
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#define HWSEM_INTC_SIFC3 BIT(3) /*!< clear semaphore 3 flag and interrupt flag */
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#define HWSEM_INTC_SIFC4 BIT(4) /*!< clear semaphore 4 flag and interrupt flag */
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#define HWSEM_INTC_SIFC5 BIT(5) /*!< clear semaphore 5 flag and interrupt flag */
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#define HWSEM_INTC_SIFC6 BIT(6) /*!< clear semaphore 6 flag and interrupt flag */
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#define HWSEM_INTC_SIFC7 BIT(7) /*!< clear semaphore 7 flag and interrupt flag */
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#define HWSEM_INTC_SIFC8 BIT(8) /*!< clear semaphore 8 flag and interrupt flag */
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#define HWSEM_INTC_SIFC9 BIT(9) /*!< clear semaphore 9 flag and interrupt flag */
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#define HWSEM_INTC_SIFC10 BIT(10) /*!< clear semaphore 10 flag and interrupt flag */
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#define HWSEM_INTC_SIFC11 BIT(11) /*!< clear semaphore 11 flag and interrupt flag */
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#define HWSEM_INTC_SIFC12 BIT(12) /*!< clear semaphore 12 flag and interrupt flag */
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#define HWSEM_INTC_SIFC13 BIT(13) /*!< clear semaphore 13 flag and interrupt flag */
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#define HWSEM_INTC_SIFC14 BIT(14) /*!< clear semaphore 14 flag and interrupt flag */
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#define HWSEM_INTC_SIFC15 BIT(15) /*!< clear semaphore 15 flag and interrupt flag */
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#define HWSEM_INTC_SIFC16 BIT(16) /*!< clear semaphore 16 flag and interrupt flag */
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#define HWSEM_INTC_SIFC17 BIT(17) /*!< clear semaphore 17 flag and interrupt flag */
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#define HWSEM_INTC_SIFC18 BIT(18) /*!< clear semaphore 18 flag and interrupt flag */
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#define HWSEM_INTC_SIFC19 BIT(19) /*!< clear semaphore 19 flag and interrupt flag */
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#define HWSEM_INTC_SIFC20 BIT(20) /*!< clear semaphore 20 flag and interrupt flag */
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#define HWSEM_INTC_SIFC21 BIT(21) /*!< clear semaphore 21 flag and interrupt flag */
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#define HWSEM_INTC_SIFC22 BIT(22) /*!< clear semaphore 22 flag and interrupt flag */
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#define HWSEM_INTC_SIFC23 BIT(23) /*!< clear semaphore 23 flag and interrupt flag */
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#define HWSEM_INTC_SIFC24 BIT(24) /*!< clear semaphore 24 flag and interrupt flag */
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#define HWSEM_INTC_SIFC25 BIT(25) /*!< clear semaphore 25 flag and interrupt flag */
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#define HWSEM_INTC_SIFC26 BIT(26) /*!< clear semaphore 26 flag and interrupt flag */
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#define HWSEM_INTC_SIFC27 BIT(27) /*!< clear semaphore 27 flag and interrupt flag */
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#define HWSEM_INTC_SIFC28 BIT(28) /*!< clear semaphore 28 flag and interrupt flag */
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#define HWSEM_INTC_SIFC29 BIT(29) /*!< clear semaphore 29 flag and interrupt flag */
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#define HWSEM_INTC_SIFC30 BIT(30) /*!< clear semaphore 30 flag and interrupt flag */
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#define HWSEM_INTC_SIFC31 BIT(31) /*!< clear semaphore 31 flag and interrupt flag */
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/* HWSEM_STAT */
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#define HWSEM_STAT_SF0 BIT(0) /*!< semaphore 0 unlock event occurs */
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#define HWSEM_STAT_SF1 BIT(1) /*!< semaphore 1 unlock event occurs */
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#define HWSEM_STAT_SF2 BIT(2) /*!< semaphore 2 unlock event occurs */
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#define HWSEM_STAT_SF3 BIT(3) /*!< semaphore 3 unlock event occurs */
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#define HWSEM_STAT_SF4 BIT(4) /*!< semaphore 4 unlock event occurs */
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#define HWSEM_STAT_SF5 BIT(5) /*!< semaphore 5 unlock event occurs */
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#define HWSEM_STAT_SF6 BIT(6) /*!< semaphore 6 unlock event occurs */
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#define HWSEM_STAT_SF7 BIT(7) /*!< semaphore 7 unlock event occurs */
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#define HWSEM_STAT_SF8 BIT(8) /*!< semaphore 8 unlock event occurs */
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#define HWSEM_STAT_SF9 BIT(9) /*!< semaphore 9 unlock event occurs */
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#define HWSEM_STAT_SF10 BIT(10) /*!< semaphore 10 unlock event occurs */
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#define HWSEM_STAT_SF11 BIT(11) /*!< semaphore 11 unlock event occurs */
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#define HWSEM_STAT_SF12 BIT(12) /*!< semaphore 12 unlock event occurs */
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#define HWSEM_STAT_SF13 BIT(13) /*!< semaphore 13 unlock event occurs */
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#define HWSEM_STAT_SF14 BIT(14) /*!< semaphore 14 unlock event occurs */
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#define HWSEM_STAT_SF15 BIT(15) /*!< semaphore 15 unlock event occurs */
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#define HWSEM_STAT_SF16 BIT(16) /*!< semaphore 16 unlock event occurs */
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#define HWSEM_STAT_SF17 BIT(17) /*!< semaphore 17 unlock event occurs */
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#define HWSEM_STAT_SF18 BIT(18) /*!< semaphore 18 unlock event occurs */
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#define HWSEM_STAT_SF19 BIT(19) /*!< semaphore 19 unlock event occurs */
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#define HWSEM_STAT_SF20 BIT(20) /*!< semaphore 20 unlock event occurs */
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#define HWSEM_STAT_SF21 BIT(21) /*!< semaphore 21 unlock event occurs */
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#define HWSEM_STAT_SF22 BIT(22) /*!< semaphore 22 unlock event occurs */
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#define HWSEM_STAT_SF23 BIT(23) /*!< semaphore 23 unlock event occurs */
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#define HWSEM_STAT_SF24 BIT(24) /*!< semaphore 24 unlock event occurs */
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#define HWSEM_STAT_SF25 BIT(25) /*!< semaphore 25 unlock event occurs */
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#define HWSEM_STAT_SF26 BIT(26) /*!< semaphore 26 unlock event occurs */
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#define HWSEM_STAT_SF27 BIT(27) /*!< semaphore 27 unlock event occurs */
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#define HWSEM_STAT_SF28 BIT(28) /*!< semaphore 28 unlock event occurs */
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#define HWSEM_STAT_SF29 BIT(29) /*!< semaphore 29 unlock event occurs */
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#define HWSEM_STAT_SF30 BIT(30) /*!< semaphore 30 unlock event occurs */
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#define HWSEM_STAT_SF31 BIT(31) /*!< semaphore 31 unlock event occurs */
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/* HWSEM_INTF */
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#define HWSEM_INTF_SIF0 BIT(0) /*!< semaphore 00 interrupt is pending */
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#define HWSEM_INTF_SIF1 BIT(1) /*!< semaphore 01 interrupt is pending */
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#define HWSEM_INTF_SIF2 BIT(2) /*!< semaphore 02 interrupt is pending */
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#define HWSEM_INTF_SIF3 BIT(3) /*!< semaphore 03 interrupt is pending */
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#define HWSEM_INTF_SIF4 BIT(4) /*!< semaphore 04 interrupt is pending */
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#define HWSEM_INTF_SIF5 BIT(5) /*!< semaphore 05 interrupt is pending */
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#define HWSEM_INTF_SIF6 BIT(6) /*!< semaphore 06 interrupt is pending */
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#define HWSEM_INTF_SIF7 BIT(7) /*!< semaphore 07 interrupt is pending */
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#define HWSEM_INTF_SIF8 BIT(8) /*!< semaphore 08 interrupt is pending */
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#define HWSEM_INTF_SIF9 BIT(9) /*!< semaphore 09 interrupt is pending */
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#define HWSEM_INTF_SIF10 BIT(10) /*!< semaphore 10 interrupt is pending */
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#define HWSEM_INTF_SIF11 BIT(11) /*!< semaphore 11 interrupt is pending */
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#define HWSEM_INTF_SIF12 BIT(12) /*!< semaphore 12 interrupt is pending */
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#define HWSEM_INTF_SIF13 BIT(13) /*!< semaphore 13 interrupt is pending */
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#define HWSEM_INTF_SIF14 BIT(14) /*!< semaphore 14 interrupt is pending */
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#define HWSEM_INTF_SIF15 BIT(15) /*!< semaphore 15 interrupt is pending */
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#define HWSEM_INTF_SIF16 BIT(16) /*!< semaphore 16 interrupt is pending */
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#define HWSEM_INTF_SIF17 BIT(17) /*!< semaphore 17 interrupt is pending */
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#define HWSEM_INTF_SIF18 BIT(18) /*!< semaphore 18 interrupt is pending */
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#define HWSEM_INTF_SIF19 BIT(19) /*!< semaphore 19 interrupt is pending */
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#define HWSEM_INTF_SIF20 BIT(20) /*!< semaphore 20 interrupt is pending */
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#define HWSEM_INTF_SIF21 BIT(21) /*!< semaphore 21 interrupt is pending */
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#define HWSEM_INTF_SIF22 BIT(22) /*!< semaphore 22 interrupt is pending */
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#define HWSEM_INTF_SIF23 BIT(23) /*!< semaphore 23 interrupt is pending */
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#define HWSEM_INTF_SIF24 BIT(24) /*!< semaphore 24 interrupt is pending */
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#define HWSEM_INTF_SIF25 BIT(25) /*!< semaphore 25 interrupt is pending */
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#define HWSEM_INTF_SIF26 BIT(26) /*!< semaphore 26 interrupt is pending */
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#define HWSEM_INTF_SIF27 BIT(27) /*!< semaphore 27 interrupt is pending */
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#define HWSEM_INTF_SIF28 BIT(28) /*!< semaphore 28 interrupt is pending */
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#define HWSEM_INTF_SIF29 BIT(29) /*!< semaphore 29 interrupt is pending */
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#define HWSEM_INTF_SIF30 BIT(30) /*!< semaphore 30 interrupt is pending */
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#define HWSEM_INTF_SIF31 BIT(31) /*!< semaphore 31 interrupt is pending */
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/* HWSEM_UNLK */
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#define HWSEM_UNLK_MID BITS(8,11) /*!< bus master ID to clear */
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#define HWSEM_UNLK_KEY BITS(16,31) /*!< HWSEM semaphore unlock key */
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/* HWSEM_KEY */
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#define HWSEM_KEY_KEY BITS(16,31) /*!< key for unlocking all semaphores of a bus master */
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/* constants definitions */
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/* HWSEM register address */
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#define HWSEM_CTL(sem) REG32(((HWSEM) + 0x0U) + 0x4U * (sem)) /*!< the address of HWSEM semaphore control register */
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#define HWSEM_RLK(sem) REG32(((HWSEM) + 0x80U) + 0x4U * (sem)) /*!< the address of HWSEM semaphore read lock register */
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/* semaphore index */
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typedef enum {
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SEM0 = 0U, /*!< semaphore 0 */
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SEM1, /*!< semaphore 1 */
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SEM2, /*!< semaphore 2 */
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SEM3, /*!< semaphore 3 */
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SEM4, /*!< semaphore 4 */
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SEM5, /*!< semaphore 5 */
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SEM6, /*!< semaphore 6 */
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SEM7, /*!< semaphore 7 */
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SEM8, /*!< semaphore 8 */
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SEM9, /*!< semaphore 9 */
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SEM10, /*!< semaphore 10 */
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SEM11, /*!< semaphore 11 */
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SEM12, /*!< semaphore 12 */
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SEM13, /*!< semaphore 13 */
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SEM14, /*!< semaphore 14 */
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SEM15, /*!< semaphore 15 */
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SEM16, /*!< semaphore 16 */
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SEM17, /*!< semaphore 17 */
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SEM18, /*!< semaphore 18 */
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SEM19, /*!< semaphore 19 */
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SEM20, /*!< semaphore 20 */
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SEM21, /*!< semaphore 21 */
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SEM22, /*!< semaphore 22 */
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SEM23, /*!< semaphore 23 */
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SEM24, /*!< semaphore 24 */
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SEM25, /*!< semaphore 25 */
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SEM26, /*!< semaphore 26 */
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SEM27, /*!< semaphore 27 */
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SEM28, /*!< semaphore 28 */
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SEM29, /*!< semaphore 29 */
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SEM30, /*!< semaphore 30 */
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SEM31 /*!< semaphore 31 */
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} hwsem_semaphore_enum;
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/* hwsem_ctlx register */
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#define CTL_PID(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to HWSEM_CTL_PID bit field */
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#define GET_CTL_PID(regval) GET_BITS((regval),0,7) /*!< get value of HWSEM_CTL_PID bit field */
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#define CTL_MID(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to HWSEM_CTL_MID bit field */
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#define GET_CTL_MID(regval) GET_BITS((regval),8,11) /*!< get value of HWSEM_CTL_MID bit field */
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#define HWSEM_LOCK HWSEM_CTL_LK /*!< HWSEM semaphore locked */
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/* hwsem_unlk register */
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#define UNLK_MID(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to HWSEM_CTL_PID bit field */
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#define UNLK_KEY(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))/*!< write value to HWSEM_CTL_PID bit field */
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/* hwsem_key register */
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#define KEY_KEY(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))/*!< write value to HWSEM_CTL_PID bit field */
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#define GET_KEY_KEY(regval) GET_BITS((regval),16,31) /*!< get value of HWSEM_CTL_PID bit field */
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/* AHB bus master ID */
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#define HWSEM_MASTER_ID 0x0BU /*!< core CM7 master ID */
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/* function declarations */
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/* lock & unlock functions */
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/* try to lock the specific semaphore by writing process ID */
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ErrStatus hwsem_lock_set(hwsem_semaphore_enum semaphore, uint8_t process);
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/* try to release the lock of the semaphore by writing process ID */
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ErrStatus hwsem_lock_release(hwsem_semaphore_enum semaphore, uint8_t process);
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/* try to lock the semaphore by reading */
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ErrStatus hwsem_lock_by_reading(hwsem_semaphore_enum semaphore);
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/* unlock all semaphores of the master ID */
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ErrStatus hwsem_unlock_all(uint16_t key);
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/* others */
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/* get process ID of the specific semaphore */
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uint32_t hwsem_process_id_get(hwsem_semaphore_enum semaphore);
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/* get master ID of the specific semaphore */
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uint32_t hwsem_master_id_get(hwsem_semaphore_enum semaphore);
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/* get the lock status of the semaphore */
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FlagStatus hwsem_lock_status_get(hwsem_semaphore_enum semaphore);
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/* set the key */
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void hwsem_key_set(uint16_t key);
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/* get the key */
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uint16_t hwsem_key_get(void);
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/* flag and interrupt functions */
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/* get the HWSEM flag status */
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FlagStatus hwsem_flag_get(hwsem_semaphore_enum semaphore);
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/* clear HWSEM flag status */
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void hwsem_flag_clear(hwsem_semaphore_enum semaphore);
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/* get HWSEM interrupt flag status */
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FlagStatus hwsem_interrupt_flag_get(hwsem_semaphore_enum semaphore);
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/* clear HWSEM interrupt flag */
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void hwsem_interrupt_flag_clear(hwsem_semaphore_enum semaphore);
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/* enable HWSEM interrupt */
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void hwsem_interrupt_enable(hwsem_semaphore_enum semaphore);
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/* disable HWSEM interrupt */
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void hwsem_interrupt_disable(hwsem_semaphore_enum semaphore);
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#endif /* GD32H7XX_HWSEM_H */
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