237 lines
15 KiB
C
237 lines
15 KiB
C
/*!
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\file gd32h7xx_mdio.h
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\brief definitions for the MDIO
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\version 2025-01-24, V1.4.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H7XX_MDIO_H
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#define GD32H7XX_MDIO_H
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#include "gd32h7xx.h"
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/* MDIO definitions */
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#define MDIO MDIO_BASE /*!< MDIO base address */
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/* registers definitions */
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#define MDIO_CTL REG32((MDIO) + 0x00000000U) /*!< MDIO control register */
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#define MDIO_RFRM REG32((MDIO) + 0x00000004U) /*!< MDIO received frame information register */
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#define MDIO_RDATA REG32((MDIO) + 0x00000008U) /*!< MDIO received data register */
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#define MDIO_RADDR REG32((MDIO) + 0x0000000CU) /*!< MDIO received address register */
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#define MDIO_TDATA REG32((MDIO) + 0x00000010U) /*!< MDIO transfer data register */
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#define MDIO_CFG REG32((MDIO) + 0x00000014U) /*!< MDIO configuration register */
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#define MDIO_STAT REG32((MDIO) + 0x00000018U) /*!< MDIO status register */
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#define MDIO_INTEN REG32((MDIO) + 0x0000001CU) /*!< MDIO interrupt enable register */
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#define MDIO_PIN REG32((MDIO) + 0x00000020U) /*!< MDIO pin value register */
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#define MDIO_TO REG32((MDIO) + 0x00000024U) /*!< MDIO timeout register */
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/* bits definitions */
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/* MDIO_CTL */
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#define MDIO_CTL_SWRST BIT(0) /*!< reset MDIO block */
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#define MDIO_CTL_PHYB BIT(1) /*!< MDIO PHY bit length */
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/* MDIO_RFRM */
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#define MDIO_RFRM_ROP BITS(0,1) /*!< received frame field OP */
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#define MDIO_RFRM_RPHY BITS(2,6) /*!< received frame field PHYADR */
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#define MDIO_RFRM_RDEV BITS(7,11) /*!< received frame field DEVADD */
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#define MDIO_RFRM_RTA BITS(12,13) /*!< received frame field TA */
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/* MDIO_RDATA */
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#define MDIO_RDATA_RDATA BITS(0,15) /*!< received frame field DATA */
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/* MDIO_RADDR */
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#define MDIO_RADDR_RADDR BITS(0,15) /*!< received frame field ADDRESS */
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/* MDIO_TDATA */
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#define MDIO_TDATA_TDATA BITS(0,15) /*!< data that is transmitted */
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/* MDIO_CFG */
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#define MDIO_CFG_PHYSW BITS(0,4) /*!< software provided PHYADR */
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#define MDIO_CFG_EPHYSEL BITS(5,9) /*!< selects expected PHYADR */
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#define MDIO_CFG_EDEVADD BITS(10,14) /*!< expected DEVADD */
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/* MDIO_STAT */
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#define MDIO_STAT_WRFRM BIT(0) /*!< set at end bit of a write data frame if DEVADD and PHYADR both match */
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#define MDIO_STAT_ADDRFRM BIT(1) /*!< set at end bit of an address frame if DEVADD and PHYADR both match */
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#define MDIO_STAT_RDINCFRM BIT(2) /*!< set at end bit of a post read increment address frame if DEVADD and PHYADR both match */
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#define MDIO_STAT_RDFRM BIT(3) /*!< set at end bit of a read data frame if DEVADD and PHYADR both match */
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#define MDIO_STAT_DEVM BIT(4) /*!< set at end bit of DEVADD if DEVADD matches */
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#define MDIO_STAT_DEVNM BIT(5) /*!< set at end bit of DEVADD if DEVADD nonmatches */
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#define MDIO_STAT_PHYM BIT(6) /*!< set at end bit of PHYADR if PHYADR matches */
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#define MDIO_STAT_PHYNM BIT(7) /*!< set at end bit of PHYADR if PHYADR nonmatches */
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#define MDIO_STAT_TANM BIT(8) /*!< set at end bit of TA of a write frame if the received TA nonmatches expected ��10�� */
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#define MDIO_STAT_TO BIT(9) /*!< timeout flag */
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#define MDIO_STAT_UDR BIT(10) /*!< transmit underrun flag */
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#define MDIO_STAT_OVR BIT(11) /*!< receive overrun flag */
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#define MDIO_STAT_RBNE BIT(13) /*!< read data buffer not empty flag */
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/* MDIO_INTEN */
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#define MDIO_INTEN_WRFRMIE BIT(0) /*!< interrupt requested when WRFRM bit becomes active */
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#define MDIO_INTEN_ADDRFRMIE BIT(1) /*!< interrupt requested when ADDRFRM bit becomes active */
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#define MDIO_INTEN_RDINCFRMIE BIT(2) /*!< interrupt requested when RDINCFRM bit becomes active */
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#define MDIO_INTEN_RDFRMIE BIT(3) /*!< interrupt requested when RDFRM bit becomes active */
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#define MDIO_INTEN_DEVMIE BIT(4) /*!< interrupt requested when DEVM bit becomes active */
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#define MDIO_INTEN_DEVNMIE BIT(5) /*!< interrupt requested when DEVNM bit becomes active */
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#define MDIO_INTEN_PHYMIE BIT(6) /*!< interrupt requested when PHYM bit becomes active */
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#define MDIO_INTEN_PHYNMIE BIT(7) /*!< interrupt requested when PHYNM bit becomes active */
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#define MDIO_INTEN_TANMIE BIT(8) /*!< interrupt requested when TANM bit becomes active */
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#define MDIO_INTEN_TOIE BIT(9) /*!< interrupt requested when TO bit becomes active */
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#define MDIO_INTEN_UDRIE BIT(10) /*!< interrupt requested when UDR bit becomes active */
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#define MDIO_INTEN_OVRIE BIT(11) /*!< interrupt requested when OVR bit becomes active */
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#define MDIO_INTEN_RBNEIE BIT(13) /*!< interrupt requested when RBNE bit becomes active */
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/* MDIO_PIN */
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#define MDIO_PIN_PHYPIN BITS(0,4) /*!< pin value read from hardware PRTADR[4:0] pins */
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/* MDIO_TO */
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#define MDIO_TO_TOEN BIT(0) /*!< timeout enable */
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#define MDIO_TO_TOCNT BITS(1,16) /*!< timeout counter */
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/* constants definitions */
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/* MDIO PHY bit length definitions */
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#define MDIO_PHY_BITS_3 MDIO_CTL_PHYB /*!< MDIO PHY uses 3 bits */
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#define MDIO_PHY_BITS_5 ((uint32_t)0x00000000U) /*!< MDIO PHY uses 5 bits */
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/* software provided PHYADR configuration definitions */
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#define CFG_PHYSW(regval) (BITS(0,4)&((uint32_t)(regval) << 0U))
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/* expected PHYADR selection definitions */
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#define CFG_EPHYSEL(regval) (BITS(5,9)&((uint32_t)(regval) << 5U))
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#define MDIO_PHYADR_HARDWARE ((uint32_t)0x00000000U) /*!< sets expected PHYADR = PHYPIN[4:0] */
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#define MDIO_PHYADR_SOFTWARE ((uint32_t)0x0000001FU) /*!< sets expected PHYADR = PHYSW[4:0] */
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#define MDIO_PHYADR_HW_SW_MIX(regval) (BITS(0,4)&((uint32_t)(regval)))/*!< software PHYADR bit select */
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/* expected DEVADD configuration definitions */
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#define CFG_EDEVADD(regval) (BITS(10,14)&((uint32_t)(regval) << 10U))
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/* get value of register bit field */
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#define GET_RFRM_ROP(regval) GET_BITS((regval),0,1) /*!< get value of MDIO_RFRM_ROP bit field */
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#define GET_RFRM_RPHY(regval) GET_BITS((regval),2,6) /*!< get value of MDIO_RFRM_RPHY bit field */
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#define GET_RFRM_RDEV(regval) GET_BITS((regval),7,11) /*!< get value of MDIO_RFRM_RDEV bit field */
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#define GET_RFRM_RTA(regval) GET_BITS((regval),12,13) /*!< get value of MDIO_RFRM_RTA bit field */
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#define GET_RDATA_RDATA(regval) GET_BITS((regval),0,15) /*!< get value of MDIO_RDATA_RDATA bit field */
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#define GET_RADDR_RADDR(regval) GET_BITS((regval),0,15) /*!< get value of MDIO_RADDR_RADDR bit field */
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#define GET_PIN_PHYPIN(regval) GET_BITS((regval),0,4) /*!< get value of MDIO_PIN_PHYPIN bit field */
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/* expected timeout configuration definitions */
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#define TO_TOCNT(regval) (BITS(1,16)&((uint32_t)(regval) << 1U))
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/* MDIO flag definitions */
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#define MDIO_FLAG_WRFRM MDIO_STAT_WRFRM /*!< a write data frame flag status */
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#define MDIO_FLAG_ADDRFRM MDIO_STAT_ADDRFRM /*!< an address frame flag status */
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#define MDIO_FLAG_RDINCFRM MDIO_STAT_RDINCFRM /*!< a post read increment address frame flag status */
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#define MDIO_FLAG_RDFRM MDIO_STAT_RDFRM /*!< a read data frame flag status */
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#define MDIO_FLAG_DEVM MDIO_STAT_DEVM /*!< a DEVADD match frame flag status */
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#define MDIO_FLAG_DEVNM MDIO_STAT_DEVNM /*!< a DEVADD nonmatch frame flag status */
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#define MDIO_FLAG_PHYM MDIO_STAT_PHYM /*!< a PHYADR match frame flag status */
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#define MDIO_FLAG_PHYNM MDIO_STAT_PHYNM /*!< a PHYADR nonmatch frame flag status */
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#define MDIO_FLAG_TANM MDIO_STAT_TANM /*!< a TA nonmatch frame flag status */
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#define MDIO_FLAG_TIMEOUT MDIO_STAT_TO /*!< timeout flag */
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#define MDIO_FLAG_TX_UNDERRUN MDIO_STAT_UDR /*!< transmit underrun flag */
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#define MDIO_FLAG_RX_OVERRUN MDIO_STAT_OVR /*!< receive overrun flag */
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#define MDIO_FLAG_RBNE MDIO_STAT_RBNE /*!< read data buffer not empty flag */
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/* MDIO interrupt definitions */
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#define MDIO_INT_WRFRM MDIO_INTEN_WRFRMIE /*!< a write data frame interrupt */
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#define MDIO_INT_ADDRFRM MDIO_INTEN_ADDRFRMIE /*!< an address frame interrupt */
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#define MDIO_INT_RDINCFRM MDIO_INTEN_RDINCFRMIE /*!< a post read increment address frame interrupt */
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#define MDIO_INT_RDFRM MDIO_INTEN_RDFRMIE /*!< a read data frame interrupt */
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#define MDIO_INT_DEVM MDIO_INTEN_DEVMIE /*!< a DEVADD match frame interrupt */
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#define MDIO_INT_DEVNM MDIO_INTEN_DEVNMIE /*!< a DEVADD nonmatch frame interrupt */
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#define MDIO_INT_PHYM MDIO_INTEN_PHYMIE /*!< a PHYADR match frame interrupt */
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#define MDIO_INT_PHYNM MDIO_INTEN_PHYNMIE /*!< a PHYADR nonmatch frame interrupt */
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#define MDIO_INT_TANM MDIO_INTEN_TANMIE /*!< a TA nonmatch frame interrupt */
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#define MDIO_INT_TIMEOUT MDIO_INTEN_TOIE /*!< a timeout interrupt */
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#define MDIO_INT_TX_UNDERRUN MDIO_INTEN_UDRIE /*!< a transmit underrun interrupt */
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#define MDIO_INT_RX_OVERRUN MDIO_INTEN_OVRIE /*!< a receive overrun interrupt */
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#define MDIO_INT_RBNE MDIO_INTEN_RBNEIE /*!< a read data buffer not empty interrupt */
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/* device type definitions */
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#define DEVADD_PMA_PMD ((uint16_t)0x0001U) /*!< device type PMA/PMD */
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#define DEVADD_WIS ((uint16_t)0x0002U) /*!< device type WIS */
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#define DEVADD_PCS ((uint16_t)0x0003U) /*!< device type PCS */
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#define DEVADD_PHY_XS ((uint16_t)0x0004U) /*!< device type PHY XS */
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#define DEVADD_DTE_XS ((uint16_t)0x0005U) /*!< device type DTE XS */
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/* function declarations */
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/* reset functions */
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/* reset MDIO */
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void mdio_deinit(void);
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/* reset MDIO block */
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void mdio_software_reset(void);
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/* fuction configuration */
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/* initialize MDIO for communication */
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uint32_t mdio_init(uint32_t phy_size, uint32_t phy_softaddr, uint32_t phy_sel, uint16_t devadd);
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/* configure MDIO phy bit length */
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void mdio_phy_length_config(uint32_t phy_bit);
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/* set the software PHYADR value */
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void mdio_soft_phyadr_set(uint32_t phy_soft);
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/* select the expected frame field PHYADR */
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void mdio_framefield_phyadr_config(uint32_t phy_sel);
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/* configure the expected frame field DEVADD */
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void mdio_framefield_devadd_config(uint16_t type);
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/* read the hardware PRTADR[4:0] value */
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uint32_t mdio_phy_pin_read(void);
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/* configure the expected frame bit timeout */
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void mdio_timeout_config(uint16_t timeout);
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/* enable MDIO frame bit timeout */
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void mdio_timeout_enable(void);
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/* disable MDIO frame bit timeout */
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void mdio_timeout_disable(void);
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/* rx & tx functions */
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/* read the received frame field OP */
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uint16_t mdio_op_receive(void);
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/* read the received frame field PHYADR */
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uint16_t mdio_phyadr_receive(void);
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/* read the received frame field DEVADD */
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uint16_t mdio_devadd_receive(void);
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/* read the received frame field TA */
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uint16_t mdio_ta_receive(void);
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/* read the received frame field DATA */
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uint16_t mdio_data_receive(void);
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/* read the received frame field ADDRESS */
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uint16_t mdio_address_receive(void);
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/* transmit the frame field DATA */
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void mdio_data_transmit(uint16_t data);
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/* interrupt & flag functions */
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/* get the flag status of the frame */
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FlagStatus mdio_flag_get(uint32_t flag);
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/* clear MDIO flag status */
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void mdio_flag_clear(uint32_t flag);
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/* enable MDIO interrupt */
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void mdio_interrupt_enable(uint32_t interrupt);
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/* disable MDIO interrupt */
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void mdio_interrupt_disable(uint32_t interrupt);
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#endif /* GD32H7XX_MDIO_H */
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