167 lines
10 KiB
C
167 lines
10 KiB
C
/*!
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\file gd32h7xx_rtdec.h
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\brief definitions for the RTDEC
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\version 2025-01-24, V1.4.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H7XX_RTDEC_H
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#define GD32H7XX_RTDEC_H
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#include "gd32h7xx.h"
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/* RTDEC definitions */
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#define RTDEC0 RTDEC_BASE /*!< RTDEC0 bsae address */
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#define RTDEC1 (RTDEC_BASE + 0x00000400U) /*!< RTDEC1 bsae address */
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#define RTDEC_AREA0 ((uint8_t)0x00U) /*!< RTDEC area0 */
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#define RTDEC_AREA1 ((uint8_t)0x01U) /*!< RTDEC area1 */
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#define RTDEC_AREA2 ((uint8_t)0x02U) /*!< RTDEC area2 */
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#define RTDEC_AREA3 ((uint8_t)0x03U) /*!< RTDEC area3 */
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#define RTDEC_ARE(rtdecx, rtdec_areax) ((rtdecx) + 0x00000030U * (rtdec_areax))
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/* registers definitions */
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#define RTDEC_ARE_CFG(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000020U) /*!< area configuration register */
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#define RTDEC_ARE_SADDR(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000024U) /*!< area start address register */
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#define RTDEC_ARE_EADDR(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000028U) /*!< area end address register */
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#define RTDEC_ARE_NONCE0(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x0000002CU) /*!< area random number register 0 */
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#define RTDEC_ARE_NONCE1(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000030U) /*!< area random number register 1 */
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#define RTDEC_ARE_KEY0(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000034U) /*!< area key register 0 */
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#define RTDEC_ARE_KEY1(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000038U) /*!< area key register 1 */
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#define RTDEC_ARE_KEY2(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x0000003CU) /*!< area key register 2 */
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#define RTDEC_ARE_KEY3(rtdecx, rtdec_areax) REG32(RTDEC_ARE((rtdecx), (rtdec_areax)) + 0x00000040U) /*!< area key register 3 */
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#define RTDEC_INTF(rtdecx) REG32((rtdecx) + 0x00000300U) /*!< interrupt flag register */
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#define RTDEC_INTC(rtdecx) REG32((rtdecx) + 0x00000304U) /*!< interrupt flag clear register */
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#define RTDEC_INTEN(rtdecx) REG32((rtdecx) + 0x00000308U) /*!< interrupt enable register */
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/* bits definitions */
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/* RTDEC_AREx_CFG */
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#define RTDEC_ARE_EN BIT(0) /*!< area real-time decryption enable bit */
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#define RTDEC_ARE_CFG_LK BIT(1) /*!< area configure lock bit */
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#define RTDEC_ARE_K_LK BIT(2) /*!< area key lock bit */
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#define RTDEC_MODE BITS(4, 5) /*!< RTDEC mode bits */
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#define RTDEC_ARE_K_CRC BITS(8, 15) /*!< 8-bit CRC of area key bits */
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#define RTDEC_ARE_FMVER BITS(16, 31) /*!< area firmware version bits */
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/* RTDEC_AREx_SADDR */
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#define RTDEC_ARE_SADDR_SADDR BITS(0, 31) /*!< area start address bits */
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/* RTDEC_AREx_EADDR */
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#define RTDEC_ARE_EADDR_EADDR BITS(0, 31) /*!< area end address bits */
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/* RTDEC_AREx_NONCE */
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#define RTDEC_ARE_NONCE_NONCE BITS(0, 31) /*!< area random number address bits */
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/* RTDEC_AREx_KEY */
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#define RTDEC_ARE_KEY_KEY BITS(0, 31) /*!< area key bits */
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/* RTDEC_INTF */
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#define RTDEC_SECEF BIT(0) /*!< security error interrupt flag */
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#define RTDEC_ECONEF BIT(1) /*!< execute-only or execute-never error interrupt flag */
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#define RTDEC_KEF BIT(2) /*!< key error interrupt flag */
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/* RTDEC_INTEN */
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#define RTDEC_SECEIE BIT(0) /*!< enable bit for security error interrupt */
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#define RTDEC_ECONEIE BIT(1) /*!< enable bit for execute-only or execute-never error interrupt */
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#define RTDEC_KEIE BIT(2) /*!< enable bit for key error interrupt */
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/* constants definitions */
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/* RTDEC modes definitions */
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#define RTDEC_MODE_SEL(regval) (RTDEC_MODE & ((uint32_t)(regval) << 4U))
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#define RTDEC_MODE_CODE_ACCESS RTDEC_MODE_SEL(0) /*!< only code accesses are decrypted */
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#define RTDEC_MODE_DATA_ACCESS RTDEC_MODE_SEL(1) /*!< only data accesses are decrypted */
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#define RTDEC_MODE_BOTH_ACCESS RTDEC_MODE_SEL(2) /*!< all read accesses are decrypted (code or data) */
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/* RTDEC interrupt flag definitions */
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#define RTDEC_INT_FLAG_SEC_ERROR RTDEC_SECEF /*!< bit constant of security error interrupt flag */
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#define RTDEC_INT_FLAG_MODE_ERROR RTDEC_ECONEF /*!< bit constant of execute-only or execute-never error interrupt flag */
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#define RTDEC_INT_FLAG_KEY_ERROR RTDEC_KEF /*!< bit constant of key error interrupt flag */
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/* RTDEC interrupt enable definitions */
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#define RTDEC_INT_SEC RTDEC_SECEIE /*!< enable bit for security error interrupt */
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#define RTDEC_INT_MODE RTDEC_ECONEIE /*!< enable bit for execute-only or execute-never error interrupt */
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#define RTDEC_INT_KEY RTDEC_KEIE /*!< enable bit for key error interrupt */
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/* RTDEC flag definitions */
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#define RTDEC_FLAG_SEC_ERROR RTDEC_SECEF /*!< bit constant of security error flag */
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#define RTDEC_FLAG_MODE_ERROR RTDEC_ECONEF /*!< bit constant of execute-only or execute-never error flag */
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#define RTDEC_FLAG_KEY_ERROR RTDEC_KEF /*!< bit constant of key error flag */
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/* structure for rtdec initialization parameter */
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typedef struct {
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uint8_t access_mode; /*!< area access mode */
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uint8_t key_crc; /*!< key CRC value */
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uint16_t fw_version; /*!< area firmware version */
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uint32_t *key; /*!< area key bits */
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uint32_t *nonce; /*!< area nonce bits */
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uint32_t start_addr; /*!< area start address */
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uint32_t end_addr; /*!< area end address */
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} rtdec_parameter_struct;
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/* function declarations */
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/* initialization functions */
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/* reset RTDEC */
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void rtdec_deinit(uint32_t rtdec_periph);
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/* initialize the parameters of RTDEC struct with default values */
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void rtdec_struct_para_init(rtdec_parameter_struct* rtdec_struct);
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/* initialize RTDEC */
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ErrStatus rtdec_init(uint32_t rtdec_periph, uint32_t rtdec_area, rtdec_parameter_struct *rtdec_struct);
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/* configure RTDEC area data attribute */
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void rtdec_config(uint32_t rtdec_periph, uint32_t rtdec_area, uint8_t access_mode, uint16_t firmware_version);
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/* configure RTDEC key or register lock */
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void rtdec_lock(uint32_t rtdec_periph, uint32_t rtdec_area, uint32_t lock_type);
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/* initialize RTDEC area address */
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void rtdec_addr_init(uint32_t rtdec_periph, uint32_t rtdec_area, uint32_t saddr, uint32_t eaddr);
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/* initialize RTDEC nonce, nonce follows little endian format */
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void rtdec_nonce_init(uint32_t rtdec_periph, uint32_t rtdec_area, uint32_t *nonce);
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/* initialize RTDEC key, key follows little endian format */
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void rtdec_key_init(uint32_t rtdec_periph, uint32_t rtdec_area, uint32_t *key);
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/* get CRC value of RTDEC key data */
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uint8_t rtdec_key_crc_get(uint32_t rtdec_periph, uint32_t rtdec_area);
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/* enable RTDEC area */
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void rtdec_enable(uint32_t rtdec_periph, uint32_t rtdec_area);
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/* disable RTDEC area */
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void rtdec_disable(uint32_t rtdec_periph, uint32_t rtdec_area);
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/* flag & interrupt functions */
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/* get RTDEC error flag */
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FlagStatus rtdec_flag_get(uint32_t rtdec_periph, uint32_t flag);
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/* clear RTDEC error flag */
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void rtdec_flag_clear(uint32_t rtdec_periph, uint32_t flag);
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/* enable RTDEC interrupt */
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void rtdec_interrupt_enable(uint32_t rtdec_periph, uint32_t interrupt);
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/* disable RTDEC interrupt */
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void rtdec_interrupt_disable(uint32_t rtdec_periph, uint32_t interrupt);
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/* get RTDEC interrupt flag */
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FlagStatus rtdec_interrupt_flag_get(uint32_t rtdec_periph, uint32_t int_flag);
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/* clear RTDEC interrupt flag */
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void rtdec_interrupt_flag_clear(uint32_t rtdec_periph, uint32_t int_flag);
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#endif /* GD32H7XX_RTDEC_H */
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