277 lines
12 KiB
C
277 lines
12 KiB
C
/*!
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\file gd32h7xx_cpdm.c
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\brief CPDM driver
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\version 2025-01-24, V1.4.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32h7xx_cpdm.h"
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#define CPDM_CPSEL_MASK ((uint32_t)0xFFFFFFF0U) /*!< CPDM output clock phase seclection mask */
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#define CPDM_DLSTCNT_MASK ((uint32_t)0xFFFF80FFU) /*!< CPDM delay step count for a uint delay UINT mask */
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#define CPDM_DLLENF_MASK ((uint32_t)0x80000000U) /*!< CPDM delay line length valid flag mask */
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#define CPDM_DLLEN_MASK ((uint32_t)0x0FFF0000U) /*!< CPDM delay line length mask */
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#define CPDM_DLLEN_OFFSET ((uint32_t)16U) /*!< CPDM delay line length offset */
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#define CPDM_DLSTCNT_OFFSET ((uint32_t)8U) /*!< CPDM delay step count for a uint delay UINT offset */
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#define CPDM_DLLEN_11 ((uint32_t)0x04000000U) /*!< CPDM delay line length bit 11 */
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#define CPDM_DLLEN_10 ((uint32_t)0x08000000U) /*!< CPDM delay line length bit 10 */
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#define CPDM_DLLEN_10_0_MASK ((uint32_t)0x7FFU) /*!< CPDM delay line length bit 10 to bit 0 mask */
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#define CPDM_MAX_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< count to judge of CPDM timeout */
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/*!
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\brief enable CPDM
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\param[in] cpdm_periph: the clock phase delay module of SDIO
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only one parameter can be selected which is shown as below:
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\arg CPDM_SDIO0: clock phase delay module of SDIO0
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\arg CPDM_SDIO1: clock phase delay module of SDIO1
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\param[out] none
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\retval none
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*/
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void cpdm_enable(uint32_t cpdm_periph)
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{
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/* enable CPDM */
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CPDM_CTL(cpdm_periph) |= (uint32_t)CPDM_CTL_CPDMEN;
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}
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/*!
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\brief disable CPDM
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\param[in] cpdm_periph: the clock phase delay module of SDIO
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only one parameter can be selected which is shown as below:
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\arg CPDM_SDIO0: clock phase delay module of SDIO0
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\arg CPDM_SDIO1: clock phase delay module of SDIO1
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\param[out] none
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\retval none
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*/
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void cpdm_disable(uint32_t cpdm_periph)
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{
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/* disable CPDM */
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CPDM_CTL(cpdm_periph) &= ~(uint32_t)CPDM_CTL_CPDMEN;
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}
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/*!
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\brief enable CPDM delay line sample module
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\param[in] cpdm_periph: the clock phase delay module of SDIO
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only one parameter can be selected which is shown as below:
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\arg CPDM_SDIO0: clock phase delay module of SDIO0
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\arg CPDM_SDIO1: clock phase delay module of SDIO1
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\param[out] none
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\retval none
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*/
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void cpdm_delayline_sample_enable(uint32_t cpdm_periph)
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{
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/* enable CPDM delay line sample module */
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CPDM_CTL(cpdm_periph) |= (uint32_t)CPDM_CTL_DLSEN;
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}
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/*!
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\brief disable CPDM delay line sample module
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\param[in] cpdm_periph: the clock phase delay module of SDIO
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only one parameter can be selected which is shown as below:
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\arg CPDM_SDIO0: clock phase delay module of SDIO0
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\arg CPDM_SDIO1: clock phase delay module of SDIO1
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\param[out] none
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\retval none
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*/
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void cpdm_delayline_sample_disable(uint32_t cpdm_periph)
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{
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/* disable CPDM delay line sample module */
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CPDM_CTL(cpdm_periph) &= ~(uint32_t)CPDM_CTL_DLSEN;
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}
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/*!
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\brief select CPDM output clock phase
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\param[in] cpdm_periph: the clock phase delay module of SDIO
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only one parameter can be selected which is shown as below:
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\arg CPDM_SDIO0: clock phase delay module of SDIO0
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\arg CPDM_SDIO1: clock phase delay module of SDIO1
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\param[in] output_clock_phase: the output clock phase, refer to cpdm_output_phase_enum
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only one parameter can be selected which is shown as below:
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\arg CPDM_OUTPUT_PHASE_SELECTION_0: output clock phase = input clock
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\arg CPDM_OUTPUT_PHASE_SELECTION_1: output clock phase = input clock + 1 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_2: output clock phase = input clock + 2 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_3: output clock phase = input clock + 3 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_4: output clock phase = input clock + 4 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_5: output clock phase = input clock + 5 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_6: output clock phase = input clock + 6 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_7: output clock phase = input clock + 7 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_8: output clock phase = input clock + 8 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_9: output clock phase = input clock + 9 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_10: output clock phase = input clock + 10 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_11: output clock phase = input clock + 11 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_12: output clock phase = input clock + 12 * UNIT delay
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\param[out] none
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\retval none
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*/
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void cpdm_output_clock_phase_select(uint32_t cpdm_periph, cpdm_output_phase_enum output_clock_phase)
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{
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uint32_t reg = 0U;
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reg = CPDM_CFG(cpdm_periph);
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reg &= CPDM_CPSEL_MASK;
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/* select CPDM output clock phase */
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reg |= output_clock_phase;
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CPDM_CFG(cpdm_periph) = (uint32_t)reg;
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}
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/*!
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\brief configure CPDM delay step
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\param[in] cpdm_periph: the clock phase delay module of SDIO
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only one parameter can be selected which is shown as below:
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\arg CPDM_SDIO0: clock phase delay module of SDIO0
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\arg CPDM_SDIO1: clock phase delay module of SDIO1
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\param[in] delay_step: 0 ~ 127
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\param[out] none
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\retval none
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*/
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void cpdm_delay_step_config(uint32_t cpdm_periph, uint8_t delay_step)
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{
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uint32_t reg = 0U;
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reg = CPDM_CFG(cpdm_periph);
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reg &= CPDM_DLSTCNT_MASK;
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/* configure delay step */
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reg |= ((uint32_t)delay_step << CPDM_DLSTCNT_OFFSET);
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CPDM_CFG(cpdm_periph) = (uint32_t)reg;
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}
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/*!
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\brief get delay line length valid flag
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\param[in] cpdm_periph: the clock phase delay module of SDIO
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only one parameter can be selected which is shown as below:
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\arg CPDM_SDIO0: clock phase delay module of SDIO0
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\arg CPDM_SDIO1: clock phase delay module of SDIO1
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\param[out] none
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\retval FlagStatus: SET or RESET
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*/
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FlagStatus cpdm_delayline_length_valid_flag_get(uint32_t cpdm_periph)
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{
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uint32_t reg = 0U;
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reg = CPDM_CFG(cpdm_periph);
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if(reg & CPDM_DLLENF_MASK) {
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return SET;
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} else {
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return RESET;
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}
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}
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/*!
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\brief get delay line length
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\param[in] cpdm_periph: the clock phase delay module of SDIO
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only one parameter can be selected which is shown as below:
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\arg CPDM_SDIO0: clock phase delay module of SDIO0
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\arg CPDM_SDIO1: clock phase delay module of SDIO1
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\param[out] none
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\retval the value of delay line length, 0x00~0xFFF
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*/
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uint16_t cpdm_delayline_length_get(uint32_t cpdm_periph)
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{
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return (uint16_t)((CPDM_CFG(cpdm_periph) & CPDM_DLLEN_MASK) >> CPDM_DLLEN_OFFSET);
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}
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/*!
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\brief configure CPDM clock output
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\param[in] cpdm_periph: the clock phase delay module of SDIO
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only one parameter can be selected which is shown as below:
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\arg CPDM_SDIO0: clock phase delay module of SDIO0
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\arg CPDM_SDIO1: clock phase delay module of SDIO1
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\param[in] output_clock_phase: the output clock phase, refer to cpdm_output_phase_enum
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only one parameter can be selected which is shown as below:
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\arg CPDM_OUTPUT_PHASE_SELECTION_0: output clock phase = input clock
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\arg CPDM_OUTPUT_PHASE_SELECTION_1: output clock phase = input clock + 1 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_2: output clock phase = input clock + 2 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_3: output clock phase = input clock + 3 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_4: output clock phase = input clock + 4 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_5: output clock phase = input clock + 5 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_6: output clock phase = input clock + 6 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_7: output clock phase = input clock + 7 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_8: output clock phase = input clock + 8 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_9: output clock phase = input clock + 9 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_10: output clock phase = input clock + 10 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_11: output clock phase = input clock + 11 * UNIT delay
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\arg CPDM_OUTPUT_PHASE_SELECTION_12: output clock phase = input clock + 12 * UNIT delay
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\param[out] none
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\retval ErrStatus: SUCCESS or ERROR
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*/
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ErrStatus cpdm_clock_output(uint32_t cpdm_periph, cpdm_output_phase_enum output_clock_phase)
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{
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uint32_t reg = 0U;
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uint32_t reg_cfg = 0U;
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uint32_t delay_count = 0U;
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uint32_t timeout = 0U;
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/* enable CPDM and delay line sample module */
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CPDM_CTL(cpdm_periph) = 0U;
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CPDM_CTL(cpdm_periph) = CPDM_CTL_CPDMEN | CPDM_CTL_DLSEN;
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/* configure CPDM output clock phase to the max value (12) */
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reg = CPDM_CFG(cpdm_periph);
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reg &= CPDM_CPSEL_MASK;
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reg |= CPDM_MAX_PHASE;
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CPDM_CFG(cpdm_periph) = (uint32_t)reg;
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for(delay_count = 0U; delay_count <= CPDM_MAX_DELAY_STEP_COUNT; delay_count++) {
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reg = CPDM_CFG(cpdm_periph);
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reg &= CPDM_DLSTCNT_MASK;
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/* configure delay line step count */
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reg |= delay_count << CPDM_DLSTCNT_OFFSET;
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CPDM_CFG(cpdm_periph) = (uint32_t)reg;
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while(RESET == (CPDM_CFG(cpdm_periph) & CPDM_CFG_DLLENF)) {
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timeout++;
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if(timeout > CPDM_MAX_TIMEOUT)
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{
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return ERROR;
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}
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}
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reg_cfg = CPDM_CFG(cpdm_periph);
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if((((reg_cfg >> CPDM_DLLEN_OFFSET) & CPDM_DLLEN_10_0_MASK) > 0U) &&
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((RESET == (reg_cfg & CPDM_DLLEN_11)) || (RESET == (reg_cfg & CPDM_DLLEN_10)))) {
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break;
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}
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}
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/* enable CPDM and delay line sample module */
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CPDM_CTL(cpdm_periph) = 0U;
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CPDM_CTL(cpdm_periph) = CPDM_CTL_CPDMEN | CPDM_CTL_DLSEN;
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/* select the output clock phase */
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reg = CPDM_CFG(cpdm_periph);
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reg &= CPDM_CPSEL_MASK;
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reg |= output_clock_phase;
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CPDM_CFG(cpdm_periph) = (uint32_t)reg;
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/* disable delay line sample module */
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CPDM_CTL(cpdm_periph) = CPDM_CTL_CPDMEN;
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return SUCCESS;
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}
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