405 lines
13 KiB
C
405 lines
13 KiB
C
/*!
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\file gd32h7xx_mdio.c
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\brief MDIO driver
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\version 2025-01-24, V1.4.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32h7xx_mdio.h"
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/*!
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\brief reset MDIO
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\param[in] none
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\param[out] none
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\retval none
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*/
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void mdio_deinit(void)
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{
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/* reset MDIO */
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rcu_periph_reset_enable(RCU_MDIORST);
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rcu_periph_reset_disable(RCU_MDIORST);
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}
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/*!
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\brief reset MDIO block
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\param[in] none
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\param[out] none
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\retval none
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*/
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void mdio_software_reset(void)
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{
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MDIO_CTL |= MDIO_CTL_SWRST;
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}
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/*!
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\brief initialize MDIO for communication
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\param[in] phy_size: PHY bit length
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only one parameter can be selected which is shown as below:
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\arg MDIO_PHY_BITS_3: PHY use 3 bits
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\arg MDIO_PHY_BITS_5: PHY use 5 bits
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\param[in] phy_softaddr: software provided PHYADR (0 - 31)
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\param[in] phy_sel: PHYADR select
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only one parameter can be selected which is shown as below:
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\arg MDIO_PHYADR_HARDWARE: sets expected PHYADR = PHYPIN[4:0]
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\arg MDIO_PHYADR_HW_SW_MIX(regval): sets Software address valid bits
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\arg MDIO_PHYADR_SOFTWARE: sets expected PHYADR = PHYSW[4:0]
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\arg other user defined value: 1 - 30
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\param[in] devadd: device type
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only one parameter can be selected which is shown as below:
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\arg DEVADD_PMA_PMD: device type PMA/PMD
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\arg DEVADD_WIS: device type WIS
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\arg DEVADD_PCS: device type PCS
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\arg DEVADD_PHY_XS: device type PHY XS
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\arg DEVADD_DTE_XS: device type DTE XS
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\param[out] none
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\retval uint32_t: the PHYADR that the device will respond to 0 - 31
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*/
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uint32_t mdio_init(uint32_t phy_size, uint32_t phy_softaddr, uint32_t phy_sel, uint16_t devadd)
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{
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uint32_t phy_addr = 0U, phy_hard = 0U;
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/* configure MDIO phy bit length */
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MDIO_CTL &= ~MDIO_CTL_PHYB;
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MDIO_CTL |= phy_size;
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/* configure the PHYADR and DEVADD */
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MDIO_CFG &= ~(MDIO_CFG_PHYSW | MDIO_CFG_EPHYSEL | MDIO_CFG_EDEVADD);
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MDIO_CFG |= CFG_PHYSW(phy_softaddr) | CFG_EPHYSEL(phy_sel) | CFG_EDEVADD(devadd);
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/* calculate the PHYADR that the device will respond to */
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phy_hard = mdio_phy_pin_read();
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phy_addr = (phy_hard & (~phy_sel)) | (phy_softaddr & phy_sel);
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return phy_addr;
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}
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/*!
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\brief configure MDIO phy bit length
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\param[in] phy_bit: PHY bit length
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only one parameter can be selected which is shown as below:
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\arg MDIO_PHY_BITS_3: PHY use 3 bits
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\arg MDIO_PHY_BITS_5: PHY use 5 bits
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\param[out] none
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\retval none
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*/
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void mdio_phy_length_config(uint32_t phy_bit)
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{
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MDIO_CTL &= ~MDIO_CTL_PHYB;
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MDIO_CTL |= phy_bit;
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}
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/*!
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\brief set the software PHYADR value
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\param[in] phy_soft: software provided PHYADR (0 - 31)
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\param[out] none
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\retval none
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*/
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void mdio_soft_phyadr_set(uint32_t phy_soft)
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{
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MDIO_CFG &= ~MDIO_CFG_PHYSW;
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MDIO_CFG |= CFG_PHYSW(phy_soft);
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}
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/*!
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\brief select the expected frame field PHYADR
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\param[in] phy_sel: PHYADR select
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only one parameter can be selected which is shown as below:
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\arg MDIO_PHYADR_HARDWARE: sets expected PHYADR = PHYPIN[4:0]
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\arg MDIO_PHYADR_SOFTWARE: sets expected PHYADR = PHYSW[4:0]
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\arg other user defined value: 1 - 30
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\param[out] none
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\retval none
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*/
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void mdio_framefield_phyadr_config(uint32_t phy_sel)
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{
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MDIO_CFG &= ~MDIO_CFG_EPHYSEL;
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MDIO_CFG |= CFG_EPHYSEL(phy_sel);
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}
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/*!
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\brief configure the expected frame field DEVADD
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\param[in] type: device type
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only one parameter can be selected which is shown as below:
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\arg DEVADD_PMA_PMD: device type PMA/PMD
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\arg DEVADD_WIS: device type WIS
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\arg DEVADD_PCS: device type PCS
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\arg DEVADD_PHY_XS: device type PHY XS
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\arg DEVADD_DTE_XS: device type DTE XS
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\param[out] none
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\retval none
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*/
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void mdio_framefield_devadd_config(uint16_t type)
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{
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MDIO_CFG &= ~MDIO_CFG_EDEVADD;
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MDIO_CFG |= CFG_EDEVADD(type);
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}
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/*!
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\brief read the hardware PRTADR[4:0] value
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\param[in] none
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\param[out] none
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\retval uint32_t: 0x0-0x1F
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*/
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uint32_t mdio_phy_pin_read(void)
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{
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return GET_PIN_PHYPIN(MDIO_PIN);
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}
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/*!
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\brief configure the expected frame bit timeout
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\param[in] timeout: timeout counter among frame bits (0 - 0xFFFF)
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\param[out] none
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\retval none
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*/
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void mdio_timeout_config(uint16_t timeout)
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{
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MDIO_TO &= ~MDIO_TO_TOCNT;
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MDIO_TO |= TO_TOCNT(timeout);
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}
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/*!
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\brief enable MDIO frame bit timeout
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\param[in] none
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\param[out] none
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\retval none
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*/
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void mdio_timeout_enable(void)
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{
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MDIO_TO |= MDIO_TO_TOEN;
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}
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/*!
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\brief disable MDIO frame bit timeout
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\param[in] none
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\param[out] none
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\retval none
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*/
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void mdio_timeout_disable(void)
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{
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MDIO_TO &= ~MDIO_TO_TOEN;
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}
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/*!
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\brief read the received frame field OP
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\param[in] none
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\param[out] none
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\retval uint16_t: 0x0-0x11
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*/
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uint16_t mdio_op_receive(void)
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{
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return (uint16_t)(GET_RFRM_ROP(MDIO_RFRM));
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}
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/*!
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\brief read the received frame field PHYADR
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\param[in] none
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\param[out] none
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\retval uint16_t: 0x0-0x1F
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*/
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uint16_t mdio_phyadr_receive(void)
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{
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return (uint16_t)(GET_RFRM_RPHY(MDIO_RFRM));
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}
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/*!
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\brief read the received frame field DEVADD
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\param[in] none
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\param[out] none
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\retval uint16_t: 0x0-0x1F
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*/
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uint16_t mdio_devadd_receive(void)
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{
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return (uint16_t)(GET_RFRM_RDEV(MDIO_RFRM));
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}
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/*!
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\brief read the received frame field TA
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\param[in] none
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\param[out] none
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\retval uint16_t: 0x0-0x11
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*/
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uint16_t mdio_ta_receive(void)
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{
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return (uint16_t)(GET_RFRM_RTA(MDIO_RFRM));
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}
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/*!
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\brief read the received frame field DATA
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\param[in] none
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\param[out] none
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\retval uint16_t: 0x0-0xFFFF
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*/
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uint16_t mdio_data_receive(void)
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{
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return (uint16_t)(GET_RDATA_RDATA(MDIO_RDATA));
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}
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/*!
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\brief read the received frame field ADDRESS
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\param[in] none
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\param[out] none
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\retval uint16_t: 0x0-0xFFFF
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*/
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uint16_t mdio_address_receive(void)
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{
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return (uint16_t)(GET_RADDR_RADDR(MDIO_RADDR));
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}
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/*!
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\brief transmit the frame field DATA
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\param[in] data: data to put in a read or post read increment address frame for transmission (0x0-0xFFFF)
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\param[out] none
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\retval none
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*/
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void mdio_data_transmit(uint16_t data)
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{
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MDIO_TDATA = (uint32_t)data;
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}
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/*!
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\brief get the flag status of the frame
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\param[in] flag: MDIO flag
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only one parameter can be selected which is shown as below:
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\arg MDIO_FLAG_WRFRM: a write data frame flag status
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\arg MDIO_FLAG_ADDRFRM: an address frame flag status
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\arg MDIO_FLAG_RDINCFRM: a post read increment address frame flag status
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\arg MDIO_FLAG_RDFRM: a read data frame flag status
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\arg MDIO_FLAG_DEVM: a DEVADD match frame flag status
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\arg MDIO_FLAG_DEVNM: a DEVADD nonmatch frame flag status
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\arg MDIO_FLAG_PHYM: a PHYADR match frame flag status
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\arg MDIO_FLAG_PHYNM: a PHYADR nonmatch frame flag status
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\arg MDIO_FLAG_TANM: a TA nonmatch frame flag status
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\arg MDIO_FLAG_TIMEOUT: timeout flag
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\arg MDIO_FLAG_TX_UNDERRUN: transmit underrun flag
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\arg MDIO_FLAG_RX_OVERRUN: receive overrun flag
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\arg MDIO_FLAG_RBNE: read data buffer not empty flag
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\param[out] none
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\retval FlagStatus: SET or RESET
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*/
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FlagStatus mdio_flag_get(uint32_t flag)
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{
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__IO uint32_t reg = 0U;
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reg = MDIO_STAT;
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if(RESET != (reg & flag)){
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return SET;
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}else{
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return RESET;
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}
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}
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/*!
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\brief clear the flag status
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\param[in] flag: MDIO flag
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one or more parameters can be selected which are shown as below:
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\arg MDIO_FLAG_WRFRM: a write data frame flag status
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\arg MDIO_FLAG_ADDRFRM: an address frame flag status
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\arg MDIO_FLAG_RDINCFRM: a post read increment address frame flag status
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\arg MDIO_FLAG_RDFRM: a read data frame flag status
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\arg MDIO_FLAG_DEVM: a DEVADD match frame flag status
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\arg MDIO_FLAG_DEVNM: a DEVADD nonmatch frame flag status
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\arg MDIO_FLAG_PHYM: a PHYADR match frame flag status
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\arg MDIO_FLAG_PHYNM: a PHYADR nonmatch frame flag status
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\arg MDIO_FLAG_TANM: a TA nonmatch frame flag status
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\arg MDIO_FLAG_TIMEOUT: timeout flag
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\arg MDIO_FLAG_TX_UNDERRUN: transmit underrun flag
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\arg MDIO_FLAG_RX_OVERRUN: receive overrun flag
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\arg MDIO_FLAG_RBNE: read data buffer not empty flag
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\param[out] none
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\retval none
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*/
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void mdio_flag_clear(uint32_t flag)
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{
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__IO uint32_t reg = 0U;
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reg = MDIO_TDATA;
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if((MDIO_FLAG_RX_OVERRUN | MDIO_FLAG_RBNE) & flag){
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(void)(MDIO_RDATA);
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}else if(MDIO_FLAG_TX_UNDERRUN & flag){
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MDIO_TDATA = reg;
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}else if((MDIO_FLAG_WRFRM | MDIO_FLAG_ADDRFRM | MDIO_FLAG_RDINCFRM | MDIO_FLAG_RDFRM
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| MDIO_FLAG_DEVM | MDIO_FLAG_DEVNM | MDIO_FLAG_PHYM | MDIO_FLAG_PHYNM | MDIO_FLAG_TIMEOUT) & flag){
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(void)(MDIO_STAT);
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} else {
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/* illegal parameters */
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}
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}
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/*!
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\brief enable MDIO interrupt
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\param[in] interrupt: MDIO interrupt
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one or more parameters can be selected which are shown as below:
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\arg MDIO_INT_WRFRM: a write data frame interrupt
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\arg MDIO_INT_ADDRFRM: an address frame interrupt
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\arg MDIO_INT_RDINCFRM: a post read increment address frame interrupt
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\arg MDIO_INT_RDFRM: a read data frame interrupt
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\arg MDIO_INT_DEVM: a DEVADD match frame interrupt
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\arg MDIO_INT_DEVNM: a DEVADD nonmatch frame interrupt
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\arg MDIO_INT_PHYM: a PHYADR match frame interrupt
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\arg MDIO_INT_PHYNM: a PHYADR nonmatch frame interrupt
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\arg MDIO_INT_TANM: a TA nonmatch frame flag interrupt
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\arg MDIO_INT_TIMEOUT: a timeout interrupt
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\arg MDIO_INT_TX_UNDERRUN: a transmit underrun interrupt
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\arg MDIO_INT_RX_OVERRUN: a receive overrun interrupt
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\arg MDIO_INT_RBNE: a read data buffer not empty interrupt
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\param[out] none
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\retval none
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*/
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void mdio_interrupt_enable(uint32_t interrupt)
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{
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MDIO_INTEN |= interrupt;
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}
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/*!
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\brief disable MDIO interrupt
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\param[in] interrupt: MDIO interrupt
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one or more parameters can be selected which are shown as below:
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\arg MDIO_INT_WRFRM: a write data frame interrupt
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\arg MDIO_INT_ADDRFRM: an address frame interrupt
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\arg MDIO_INT_RDINCFRM: a post read increment address frame interrupt
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\arg MDIO_INT_RDFRM: a read data frame interrupt
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\arg MDIO_INT_DEVM: a DEVADD match frame interrupt
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\arg MDIO_INT_DEVNM: a DEVADD nonmatch frame interrupt
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\arg MDIO_INT_PHYM: a PHYADR match frame interrupt
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\arg MDIO_INT_PHYNM: a PHYADR nonmatch frame interrupt
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\arg MDIO_INT_TANM: a TA nonmatch frame flag interrupt
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\arg MDIO_INT_TIMEOUT: a timeout interrupt
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\arg MDIO_INT_TX_UNDERRUN: a transmit underrun interrupt
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\arg MDIO_INT_RX_OVERRUN: a receive overrun interrupt
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\arg MDIO_INT_RBNE: a read data buffer not empty interrupt
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\param[out] none
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\retval none
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*/
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void mdio_interrupt_disable(uint32_t interrupt)
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{
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MDIO_INTEN &= ~(interrupt);
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}
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