107 lines
5.8 KiB
C
107 lines
5.8 KiB
C
/*!
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\file gd32h7xx_cpdm.h
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\brief definitions for the CPDM
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\version 2025-01-24, V1.4.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H7XX_CPDM_H
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#define GD32H7XX_CPDM_H
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#include "gd32h7xx.h"
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/* CPDM definitions */
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#define CPDM_SDIO0 (SDIO0 + 0x00001000U) /*!< SDIO0 CPDM base address */
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#define CPDM_SDIO1 (SDIO1 + 0x00000400U) /*!< SDIO1 CPDM base address */
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/* registers definitions */
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#define CPDM_CTL(cpdmx) REG32((cpdmx) + 0x00000000U) /*!< CPDM control register */
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#define CPDM_CFG(cpdmx) REG32((cpdmx) + 0x00000004U) /*!< CPDM configuration register */
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/* bits definitions */
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/* CPDM_CTL */
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#define CPDM_CTL_CPDMEN BIT(0) /*!< CPDM enable */
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#define CPDM_CTL_DLSEN BIT(1) /*!< CPDM delay line sample module enable */
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/* CPDM_CFG */
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#define CPDM_CFG_CPSEL BITS(0,3) /*!< select the phase of the output clock */
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#define CPDM_CFG_DLSTCNT BITS(8,14) /*!< define a delay step count for a unit delay UNIT */
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#define CPDM_CFG_DLLEN BITS(16,27) /*!< delay line length */
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#define CPDM_CFG_DLLENF BIT(31) /*!< valid mark of delay line length */
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/* constants definitions */
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/* output clock phase selection enum definition */
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typedef enum
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{
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CPDM_OUTPUT_PHASE_SELECTION_0 = 0, /*!< output clock phase = input clock */
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CPDM_OUTPUT_PHASE_SELECTION_1, /*!< output clock phase = input clock + 1 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_2, /*!< output clock phase = input clock + 2 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_3, /*!< output clock phase = input clock + 3 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_4, /*!< output clock phase = input clock + 4 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_5, /*!< output clock phase = input clock + 5 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_6, /*!< output clock phase = input clock + 6 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_7, /*!< output clock phase = input clock + 7 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_8, /*!< output clock phase = input clock + 8 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_9, /*!< output clock phase = input clock + 9 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_10, /*!< output clock phase = input clock + 10 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_11, /*!< output clock phase = input clock + 11 * UNIT delay */
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CPDM_OUTPUT_PHASE_SELECTION_12, /*!< output clock phase = input clock + 12 * UNIT delay */
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}cpdm_output_phase_enum;
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#define CPDM_MAX_DELAY_STEP_COUNT ((uint32_t)0x0000007FU) /*!< max UNIT value */
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#define CPDM_MAX_PHASE ((uint32_t)0x0000000CU) /*!< max select value of the phase */
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/* function declarations */
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/* deinitialization and initialization functions */
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/* enable CPDM */
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void cpdm_enable(uint32_t cpdm_periph);
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/* disable CPDM */
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void cpdm_disable(uint32_t cpdm_periph);
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/* enable CPDM delay line sample module */
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void cpdm_delayline_sample_enable(uint32_t cpdm_periph);
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/* disable CPDM delay line sample module */
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void cpdm_delayline_sample_disable(uint32_t cpdm_periph);
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/* output clock configuration functions */
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/* select CPDM output clock phase */
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void cpdm_output_clock_phase_select(uint32_t cpdm_periph, cpdm_output_phase_enum output_clock_phase);
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/* configure CPDM delay step */
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void cpdm_delay_step_config(uint32_t cpdm_periph, uint8_t delay_step);
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/* get delay line length valid flag */
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FlagStatus cpdm_delayline_length_valid_flag_get(uint32_t cpdm_periph);
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/* get delay line length */
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uint16_t cpdm_delayline_length_get(uint32_t cpdm_periph);
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/* clock output function */
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/* configure CPDM clock output */
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ErrStatus cpdm_clock_output(uint32_t cpdm_periph, cpdm_output_phase_enum output_clock_phase);
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#endif /* GD32H7XX_CPDM_H */
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