535 lines
37 KiB
C
535 lines
37 KiB
C
/*!
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\file gd32h7xx_sdio.h
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\brief definitions for the SDIO
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\version 2025-01-24, V1.4.0, firmware for GD32H7xx
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*/
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/*
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Copyright (c) 2025, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32H7XX_SDIO_H
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#define GD32H7XX_SDIO_H
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#include "gd32h7xx.h"
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/* SDIO definitions */
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#define SDIO0 (SDIO_BASE + 0x09FE4C00U)
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#define SDIO1 (SDIO_BASE)
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/* registers definitions */
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#define SDIO_PWRCTL(sdiox) REG32((sdiox) + 0x00000000U) /*!< SDIO power control register */
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#define SDIO_CLKCTL(sdiox) REG32((sdiox) + 0x00000004U) /*!< SDIO clock control register */
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#define SDIO_CMDAGMT(sdiox) REG32((sdiox) + 0x00000008U) /*!< SDIO command argument register */
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#define SDIO_CMDCTL(sdiox) REG32((sdiox) + 0x0000000CU) /*!< SDIO command control register */
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#define SDIO_RSPCMDIDX(sdiox) REG32((sdiox) + 0x00000010U) /*!< SDIO command index response register */
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#define SDIO_RESP0(sdiox) REG32((sdiox) + 0x00000014U) /*!< SDIO response register 0 */
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#define SDIO_RESP1(sdiox) REG32((sdiox) + 0x00000018U) /*!< SDIO response register 1 */
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#define SDIO_RESP2(sdiox) REG32((sdiox) + 0x0000001CU) /*!< SDIO response register 2 */
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#define SDIO_RESP3(sdiox) REG32((sdiox) + 0x00000020U) /*!< SDIO response register 3 */
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#define SDIO_DATATO(sdiox) REG32((sdiox) + 0x00000024U) /*!< SDIO data timeout register */
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#define SDIO_DATALEN(sdiox) REG32((sdiox) + 0x00000028U) /*!< SDIO data length register */
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#define SDIO_DATACTL(sdiox) REG32((sdiox) + 0x0000002CU) /*!< SDIO data control register */
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#define SDIO_DATACNT(sdiox) REG32((sdiox) + 0x00000030U) /*!< SDIO data counter register */
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#define SDIO_STAT(sdiox) REG32((sdiox) + 0x00000034U) /*!< SDIO status register */
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#define SDIO_INTC(sdiox) REG32((sdiox) + 0x00000038U) /*!< SDIO interrupt clear register */
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#define SDIO_INTEN(sdiox) REG32((sdiox) + 0x0000003CU) /*!< SDIO interrupt enable register */
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#define SDIO_ACKTO(sdiox) REG32((sdiox) + 0x00000040U) /*!< SDIO FIFO ACK timeout register */
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#define SDIO_FIFO(sdiox) REG32((sdiox) + 0x00000080U) /*!< SDIO FIFO data register */
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#define SDIO_IDMACTL(sdiox) REG32((sdiox) + 0x00000050U) /*!< SDIO FIFO internal DMA control register */
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#define SDIO_IDMASIZE(sdiox) REG32((sdiox) + 0x00000054U) /*!< SDIO FIFO internal DMA buffer size register */
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#define SDIO_IDMAADDR0(sdiox) REG32((sdiox) + 0x00000058U) /*!< SDIO FIFO internal DMA buffer 0 base address register */
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#define SDIO_IDMAADDR1(sdiox) REG32((sdiox) + 0x0000005CU) /*!< SDIO FIFO internal DMA buffer 1 base address register */
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/* bits definitions */
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/* SDIO_PWRCTL */
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#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */
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#define SDIO_PWRCTL_VSSTART BIT(2) /*!< voltage switch start bit */
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#define SDIO_PWRCTL_VSEN BIT(3) /*!< voltage switch enable bit */
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#define SDIO_PWRCTL_DIRPS BIT(4) /*!< data and command direction polarity selection bit */
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/* SDIO_CLKCTL */
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#define SDIO_CLKCTL_DIV BITS(0,9) /*!< clock division */
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#define SDIO_CLKCTL_CLKPWRSAV BIT(12) /*!< SDIO_CLK clock dynamic switch on/off for power saving */
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#define SDIO_CLKCTL_BUSMODE BITS(14,15) /*!< SDIO card bus mode control bit */
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#define SDIO_CLKCTL_CLKEDGE BIT(16) /*!< command and data SDIO_CLK dephasing selection bit */
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#define SDIO_CLKCTL_HWEN BIT(17) /*!< hardware flow control enable bit */
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#define SDIO_CLKCTL_DRSEL BIT(18) /*!< data rate selection bit */
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#define SDIO_CLKCTL_BUSSP BIT(19) /*!< bus speed mode selection bit */
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#define SDIO_CLKCTL_RCLK BITS(20,21) /*!< receive clock selection bits */
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/* SDIO_CMDAGMT */
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#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */
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/* SDIO_CMDCTL */
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#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */
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#define SDIO_CMDCTL_TREN BIT(6) /*!< data transfer mode enable bit */
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#define SDIO_CMDCTL_TRSTOP BIT(7) /*!< data transfer stop bit */
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#define SDIO_CMDCTL_CMDRESP BITS(8,9) /*!< waits command response type bits */
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#define SDIO_CMDCTL_INTWAIT BIT(10) /*!< interrupt wait instead of timeout */
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#define SDIO_CMDCTL_WAITDEND BIT(11) /*!< waits for ends of data transfer */
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#define SDIO_CMDCTL_CSMEN BIT(12) /*!< command state machine (CSM) enable bit */
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#define SDIO_CMDCTL_HOLD BIT(13) /*!< hold DSM transmission and reception of new data block */
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#define SDIO_CMDCTL_BOOTMOD BIT(14) /*!< boot mode selection bit */
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#define SDIO_CMDCTL_BOOTMODEN BIT(15) /*!< boot mode procedure enable bit */
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#define SDIO_CMDCTL_CMDSR BIT(16) /*!< suspend or resume command and signals interrupt period start/end bit */
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/* SDIO_DATATO */
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#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */
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/* SDIO_DATALEN */
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#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */
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/* SDIO_DATACTL */
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#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */
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#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */
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#define SDIO_DATACTL_TRANSMOD BITS(2,3) /*!< data transfer mode */
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#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */
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#define SDIO_DATACTL_ACKEN BIT(12) /*!< boot acknowledgment enable bit */
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#define SDIO_DATACTL_FIFOREST BIT(13) /*!< FIFO buffer reset, flush all data */
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/* SDIO_STAT */
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#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */
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#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */
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#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */
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#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */
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#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */
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#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */
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#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */
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#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */
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#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT is zero) */
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#define SDIO_STAT_DATHOLD BIT(9) /*!< data transfer hold */
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#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */
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#define SDIO_STAT_DATABOR BIT(11) /*!< data transfer aborted by CMD12 */
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#define SDIO_STAT_CMDSTA BIT(12) /*!< command path active state */
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#define SDIO_STAT_DATSTA BIT(13) /*!< data path active state */
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#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty */
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#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full */
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#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */
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#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */
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#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */
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#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */
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#define SDIO_STAT_DAT0BSY BIT(20) /*!< DAT0 line signal keep busy */
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#define SDIO_STAT_DAT0BSYEND BIT(21) /*!< DAT0 line signal changed from busy to ready */
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#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */
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#define SDIO_STAT_ACKFAIL BIT(23) /*!< boot acknowledgment received and check fail */
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#define SDIO_STAT_ACKTO BIT(24) /*!< boot acknowledgment timeout */
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#define SDIO_STAT_VSEND BIT(25) /*!< voltage switch critical timing section end */
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#define SDIO_STAT_CLKSTOP BIT(26) /*!< SDIO_CLK stopped in voltage switch procedure */
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#define SDIO_STAT_IDMERR BIT(27) /*!< IDMA transfer error */
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#define SDIO_STAT_IDMAEND BIT(28) /*!< IDMA transfer end */
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/* SDIO_INTC */
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#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */
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#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */
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#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */
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#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */
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#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */
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#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */
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#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */
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#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */
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#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */
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#define SDIO_INTC_DATHOLDC BIT(9) /*!< DATHOLD flag clear bit */
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#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */
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#define SDIO_INTC_DATABORC BIT(11) /*!< DATABOR flag clear bit */
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#define SDIO_INTC_DAT0BSYENDC BIT(21) /*!< DAT0BSYEND flag clear bit */
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#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */
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#define SDIO_INTC_ACKFAILC BIT(23) /*!< ACKFAIL flag clear bit */
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#define SDIO_INTC_ACKTOC BIT(24) /*!< ACKTO flag clear bit */
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#define SDIO_INTC_VSENDC BIT(25) /*!< VSEND flag clear bit */
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#define SDIO_INTC_CLKSTOPC BIT(26) /*!< CLKSTOP flag clear bit */
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#define SDIO_INTC_IDMERRC BIT(27) /*!< IDMERR flag clear bit */
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#define SDIO_INTC_IDMAENDC BIT(28) /*!< IDMAEND flag clear bit */
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/* SDIO_INTEN */
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#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */
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#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */
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#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */
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#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */
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#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */
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#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */
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#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */
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#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */
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#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */
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#define SDIO_INTEN_DATHOLDIE BIT(9) /*!< data transfer hold interrupt enable */
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#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */
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#define SDIO_INTEN_DATABORIE BIT(11) /*!< data transfer abort interrupt enable */
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#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */
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#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */
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#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */
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#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */
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#define SDIO_INTEN_DAT0BSYENDIE BIT(21) /*!< DAT0 line signal changed from busy to ready interrupt enable */
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#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */
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#define SDIO_INTEN_ACKFAILIE BIT(23) /*!< boot acknowledgment received and check fail interrupt enable */
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#define SDIO_INTEN_ACKTOIE BIT(24) /*!< boot acknowledgment timeout enable */
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#define SDIO_INTEN_VSENDIE BIT(25) /*!< voltage switch critical timing section end interrupt enable */
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#define SDIO_INTEN_CLKSTOPIE BIT(26) /*!< voltage Switch clock stopped interrupt enable */
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#define SDIO_INTEN_IDMAERRIE BIT(27) /*!< IDMA transfer error interrupt enable */
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#define SDIO_INTEN_IDMAENDIE BIT(28) /*!< IDMA transfer end interrupt enable */
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/* SDIO_ACKTO */
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#define SDIO_ACKTO_ACKTO BITS(0, 24) /*!< boot ACK timeout period */
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/* SDIO_FIFO */
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#define SDIO_FIFO_FIFODT BITS(0, 31) /*!< receive FIFO data or transmit FIFO data */
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/* SDIO_IDMACTL */
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#define SDIO_IDMACTL_IDMAEN BIT(0) /*!< FIFO IDMA enable bit */
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#define SDIO_IDMACTL_BUFMOD BIT(1) /*!< double buffer mode enable bit */
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#define SDIO_IDMACTL_BUFSEL BIT(2) /*!< IDMA double buffer selection bit */
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/* SDIO_IDMASIZE */
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#define SDIO_IDMASIZE_IDMASIZE BITS(5, 12) /*!< number of bytes per buffer, buffer size = number*32 */
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/* SDIO_IDMAADDR0 */
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#define SDIO_IDMAADDR0_IDMAADDR0 BITS(0, 31) /*!< IDMA buffer 0 base address, is a multiple of 8 */
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/* SDIO_IDMAADDR1 */
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#define SDIO_IDMAADDR1_IDMAADDR1 BITS(0, 31) /*!< IDMA buffer 1 base address, is a multiple of 8 */
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/* constants definitions */
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/* SDIO power control */
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#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
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#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */
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#define SDIO_POWER_CYCLE PWRCTL_PWRCTL(2) /*!< SDIO power cycle */
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#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */
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/* SDIO receive clock selection */
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#define CLKCTL_RECEICECLOCK(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20))
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#define SDIO_RECEIVECLOCK_INCLK CLKCTL_RECEICECLOCK(0) /*!< select SDIO_IN_CLK clock */
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#define SDIO_RECEIVECLOCK_CLKIN CLKCTL_RECEICECLOCK(1) /*!< select SDIO_CLKIN clock */
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#define SDIO_RECEIVECLOCK_FBCLK CLKCTL_RECEICECLOCK(2) /*!< select SDIO_FB_CLK clock */
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/* SDIO card bus speed control */
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#define SDIO_BUSSPEED_LOW (uint32_t)0x00000000U /*!< DS, HS, SDR12, SDR25 bus speed */
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#define SDIO_BUSSPEED_HIGH SDIO_CLKCTL_BUSSP /*!< SDR50, SDR104, DDR50 bus speed */
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/* SDIO data rate selection */
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#define SDIO_DATA_RATE_SDR (uint32_t)0x00000000U /*!< SDR selected */
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#define SDIO_DATA_RATE_DDR SDIO_CLKCTL_DRSEL /*!< DDR selected */
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/* SDIO_CLK clock edge selection */
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#define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U /*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */
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#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */
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/* SDIO_CLK clock dynamic switch on/off for power saving */
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#define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U /*!< SDIO_CLK clock is always on */
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#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */
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/* SDIO card bus mode control */
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#define CLKCTL_BUSMODE(regval) (BITS(14, 15) & ((uint32_t)(regval) << 14))
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#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */
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#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */
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#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */
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/* SDIO direction polarity of data and command */
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#define SDIO_DIRECTION_SIGNAL_LOW (uint32_t)0x00000000U /*!< direction signal is low, the voltage transceiver IOs driven as output */
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#define SDIO_DIRECTION_SIGNAL_HIGH SDIO_PWRCTL_DIRPS /*!< direction signal is high, the voltage transceiver IOs driven as output */
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/* SDIO boot mode */
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#define SDIO_BOOTMODE_NORMAL (uint32_t)0x00000000U /*!< normal boot mode */
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#define SDIO_BOOTMODE_ALTERNATIVE SDIO_CMDCTL_BOOTMOD /*!< alternative boot mode */
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/* SDIO command response type */
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#define CMDCTL_CMDRESP(regval) (BITS(8, 9) & ((uint32_t)(regval) << 8))
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#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */
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#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */
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#define SDIO_RESPONSETYPE_SHORT_NOCRC CMDCTL_CMDRESP(2) /*!< short response without CRC */
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#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */
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/* command state machine wait type */
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#define SDIO_WAITTYPE_NO (uint32_t)0x00000000U /*!< not wait interrupt */
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#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */
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#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */
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/* command type */
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#define SDIO_CMDTYPE_NO (uint32_t)0x00000000U /*!< just a command */
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#define SDIO_CMDTYPE_TRANSFER SDIO_CMDCTL_TREN /*!< command for transfer */
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#define SDIO_CMDTYPE_TRANSFERSTOP SDIO_CMDCTL_TRSTOP /*!< commang for stopping transfer */
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#define SDIO_CMDTYPE_SUSPEND SDIO_CMDCTL_CMDSR /*!< suspend command, or resume command */
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/* short response and each part of the long response */
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#define SDIO_RESPONSE0 (uint32_t)0x00000000U /*!< card response[31:0]/card response[127:96] */
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#define SDIO_RESPONSE1 (uint32_t)0x00000001U /*!< card response[95:64] */
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#define SDIO_RESPONSE2 (uint32_t)0x00000002U /*!< card response[63:32] */
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#define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */
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/* SDIO data block size */
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#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
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#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */
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#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */
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#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */
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#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */
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#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */
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#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */
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#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */
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#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */
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#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */
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#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */
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#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */
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#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */
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#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */
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#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */
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#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */
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/* SDIO data transfer mode */
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#define DATACTL_TRANSMODE(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
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#define SDIO_TRANSMODE_BLOCKCOUNT DATACTL_TRANSMODE(0) /*!< block count data transfer */
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#define SDIO_TRANSMODE_MULTIBYTE DATACTL_TRANSMODE(1) /*!< multibyte data transfer (only SD/SD I/O) */
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#define SDIO_TRANSMODE_STREAM DATACTL_TRANSMODE(2) /*!< stream transfer (only eMMC) */
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#define SDIO_TRANSMODE_BLOCKCMD12 DATACTL_TRANSMODE(3) /*!< block data transfer ends with CMD12 */
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/* SDIO data transfer direction */
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#define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U /*!< write data to card */
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#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */
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/* SDIO idma buffer mode */
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#define SDIO_IDMA_SINGLE_BUFFER (uint32_t)0x00000000U /*!< single buffer mode */
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#define SDIO_IDMA_DOUBLE_BUFFER SDIO_IDMACTL_BUFMOD /*!< double buffer mode */
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/* SDIO idma buffer selection */
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#define SDIO_IDMA_BUFFER0 (uint32_t)0x00000000U /*!< select buffer0 */
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#define SDIO_IDMA_BUFFER1 SDIO_IDMACTL_BUFSEL /*!< select buffer1 */
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/* constants definitions */
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/* SDIO flags */
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#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */
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#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */
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#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */
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#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */
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#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */
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#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */
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#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */
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#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */
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#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT is zero) flag */
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#define SDIO_FLAG_DTHOLD BIT(9) /*!< data transfer hold flag */
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#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */
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#define SDIO_FLAG_DTABORT BIT(11) /*!< data transfer aborted by CMD12 flag */
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#define SDIO_FLAG_CMDSTA BIT(12) /*!< command path active state flag */
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#define SDIO_FLAG_DATSTA BIT(13) /*!< data path active state flag */
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#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */
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#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */
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#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */
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#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */
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#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */
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#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */
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#define SDIO_FLAG_DAT0BSY BIT(20) /*!< DAT0 line signal keep busy flag */
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#define SDIO_FLAG_DAT0BSYEND BIT(21) /*!< DAT0 line signal changed from busy to ready flag */
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#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */
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#define SDIO_FLAG_ACKFAIL BIT(23) /*!< boot acknowledgment received and check fail flag */
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#define SDIO_FLAG_ACKTO BIT(24) /*!< boot acknowledgment timeout flag */
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#define SDIO_FLAG_VOLSWEND BIT(25) /*!< voltage switch critical timing section end flag */
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#define SDIO_FLAG_CLKSTOP BIT(26) /*!< SDIO_CLK stopped in voltage switch procedure flag */
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#define SDIO_FLAG_IDMAERR BIT(27) /*!< IDMA transfer error flag */
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#define SDIO_FLAG_IDMAEND BIT(28) /*!< IDMA transfer end flag */
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/* SDIO interrupt enable or disable */
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#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */
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#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */
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#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */
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#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */
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#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */
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#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */
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#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */
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#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */
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#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */
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#define SDIO_INT_DTHOLD BIT(9) /*!< SDIO DTHOLD interrupt */
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#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */
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#define SDIO_INT_DTABORT BIT(11) /*!< SDIO DTABORT interrupt */
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#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */
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#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */
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#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */
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#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */
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#define SDIO_INT_DAT0BSYEND BIT(21) /*!< SDIO DAT0BSYEND interrupt */
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#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */
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#define SDIO_INT_ACKFAIL BIT(23) /*!< SDIO ACKFAIL interrupt */
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#define SDIO_INT_ACKTO BIT(24) /*!< SDIO ACKTO interrupt */
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#define SDIO_INT_VOLSWEND BIT(25) /*!< SDIO VOLSWEND interrupt */
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#define SDIO_INT_CLKSTOP BIT(26) /*!< SDIO CLKSTOP interrupt */
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#define SDIO_INT_IDMAERR BIT(27) /*!< SDIO IDMAERR interrupt */
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#define SDIO_INT_IDMAEND BIT(28) /*!< SDIO IDMAEND interrupt */
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/* SDIO interrupt flag: enable or disable */
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#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt flag */
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#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt flag */
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#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt flag */
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#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt flag */
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#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt flag */
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#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt flag */
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#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt flag */
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#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt flag */
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#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt flag */
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#define SDIO_INT_FLAG_DTHOLD BIT(9) /*!< SDIO DTHOLD interrupt flag */
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#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt flag */
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#define SDIO_INT_FLAG_DTABORT BIT(11) /*!< SDIO DTABORT interrupt flag */
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#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt flag */
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#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt flag */
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#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt flag */
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#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt flag */
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#define SDIO_INT_FLAG_DAT0BSYEND BIT(21) /*!< SDIO DAT0BSYEND interrupt flag */
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#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt flag */
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#define SDIO_INT_FLAG_ACKFAIL BIT(23) /*!< SDIO ACKFAIL interrupt flag */
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#define SDIO_INT_FLAG_ACKTO BIT(24) /*!< SDIO ACKTO interrupt flag */
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#define SDIO_INT_FLAG_VOLSWEND BIT(25) /*!< SDIO VOLSWEND interrupt flag */
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#define SDIO_INT_FLAG_CLKSTOP BIT(26) /*!< SDIO CLKSTOP interrupt flag */
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#define SDIO_INT_FLAG_IDMAERR BIT(27) /*!< SDIO IDMAERR interrupt flag */
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#define SDIO_INT_FLAG_IDMAEND BIT(28) /*!< SDIO IDMAEND interrupt flag */
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/* SDIO read wait type */
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#define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U /*!< read wait control using SDIO_DAT[2] */
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#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */
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/* function declarations */
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/* de/initialization functions, hardware clock, bus mode, power_state and SDIO clock configuration */
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/* deinitialize the SDIO */
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void sdio_deinit(uint32_t sdio_periph);
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/* configure the SDIO clock */
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void sdio_clock_config(uint32_t sdio_periph, uint32_t clock_edge, uint32_t clock_powersave, uint32_t clock_division);
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/* set receive clock */
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void sdio_clock_receive_set(uint32_t sdio_periph, uint32_t clock_receive);
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/* enable hardware clock control */
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void sdio_hardware_clock_enable(uint32_t sdio_periph);
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/* disable hardware clock control */
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void sdio_hardware_clock_disable(uint32_t sdio_periph);
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/* set different SDIO card bus mode */
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void sdio_bus_mode_set(uint32_t sdio_periph, uint32_t bus_mode);
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/* set SDIO bus speed */
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void sdio_bus_speed_set(uint32_t sdio_periph, uint32_t bus_speed);
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/* set SDIO data rate */
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void sdio_data_rate_set(uint32_t sdio_periph, uint32_t data_rate);
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/* set direction polarity of data and command */
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void sdio_direction_polarity_set(uint32_t sdio_periph, uint32_t dirpl);
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/* set the SDIO power state */
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void sdio_power_state_set(uint32_t sdio_periph, uint32_t power_state);
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/* get the SDIO power state */
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uint32_t sdio_power_state_get(uint32_t sdio_periph);
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/* configure the command index, argument, command type, response type, wait type and CSM(command state machine) to send command functions */
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/* configure the command and response */
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void sdio_command_response_config(uint32_t sdio_periph, uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type);
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/* set the command state machine wait type */
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void sdio_wait_type_set(uint32_t sdio_periph, uint32_t wait_type);
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/* enable the CSM transfer command mode(treats the command as a data transfer command) */
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void sdio_trans_start_enable(uint32_t sdio_periph);
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/* disable the CSM transfer command mode(treats the command as a data transfer command) */
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void sdio_trans_start_disable(uint32_t sdio_periph);
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/* enable the CSM stop command mode(treats the command as a data stop transfer command) */
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void sdio_trans_stop_enable(uint32_t sdio_periph);
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/* disable the CSM stop command mode(treats the command as a data stop transfer command) */
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void sdio_trans_stop_disable(uint32_t sdio_periph);
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/* enable the CSM(command state machine) */
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void sdio_csm_enable(uint32_t sdio_periph);
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/* disable the CSM(command state machine) */
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void sdio_csm_disable(uint32_t sdio_periph);
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/* get the last response command index */
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uint8_t sdio_command_index_get(uint32_t sdio_periph);
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/* get the response for the last received command */
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uint32_t sdio_response_get(uint32_t sdio_periph, uint32_t sdio_responsex);
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/* enable the data hold */
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void sdio_hold_enable(uint32_t sdio_periph);
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/* disable the data hold */
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void sdio_hold_disable(uint32_t sdio_periph);
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/* enable the SDIO suspend mode (the CSM treats the command as a Suspend command or Resume command) */
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void sdio_suspend_enable(uint32_t sdio_periph);
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/* disable the SDIO suspend mode (the CSM treats the command as a Suspend command or Resume command) */
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void sdio_suspend_disable(uint32_t sdio_periph);
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/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer functions */
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/* configure the data timeout, data length and data block size */
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void sdio_data_config(uint32_t sdio_periph, uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize);
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/* configure the data transfer mode and direction */
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void sdio_data_transfer_config(uint32_t sdio_periph, uint32_t transfer_mode, uint32_t transfer_direction);
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/* enable the DSM(data state machine) for data transfer */
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void sdio_dsm_enable(uint32_t sdio_periph);
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/* disable the DSM(data state machine) for data transfer */
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void sdio_dsm_disable(uint32_t sdio_periph);
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/* write data(one word) to the transmit FIFO */
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void sdio_data_write(uint32_t sdio_periph, uint32_t data);
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/* read data(one word) from the receive FIFO */
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uint32_t sdio_data_read(uint32_t sdio_periph);
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/* get the number of remaining data bytes to be transferred to card */
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uint32_t sdio_data_counter_get(uint32_t sdio_periph);
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/* enable the FIFO buffer reset */
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void sdio_fifo_reset_enable(uint32_t sdio_periph);
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/* disable the FIFO buffer reset */
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void sdio_fifo_reset_disable(uint32_t sdio_periph);
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/* configure the IMDA */
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/* set IDMA buffer mode and size */
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void sdio_idma_set(uint32_t sdio_periph, uint32_t buffer_mode, uint32_t buffer_size);
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/* set IDMA buffer0 address */
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void sdio_idma_buffer0_address_set(uint32_t sdio_periph, uint32_t buffer_address);
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/* set IDMA buffer1 address */
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void sdio_idma_buffer1_address_set(uint32_t sdio_periph, uint32_t buffer_address);
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/* get the IDMA double buffer address selection bit */
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uint32_t sdio_buffer_selection_get(uint32_t sdio_periph);
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/* select IDMA buffer */
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void sdio_idma_buffer_select(uint32_t sdio_periph, uint32_t buffer_select);
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/* enable the IDMA request for SDIO */
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void sdio_idma_enable(uint32_t sdio_periph);
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/* disable the IDMA request for SDIO */
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void sdio_idma_disable(uint32_t sdio_periph);
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/* flag and interrupt functions */
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/* get the flags state of SDIO */
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FlagStatus sdio_flag_get(uint32_t sdio_periph, uint32_t flag);
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/* clear the pending flags of SDIO */
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void sdio_flag_clear(uint32_t sdio_periph, uint32_t flag);
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/* enable the SDIO interrupt */
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void sdio_interrupt_enable(uint32_t sdio_periph, uint32_t int_flag);
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/* disable the SDIO interrupt */
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void sdio_interrupt_disable(uint32_t sdio_periph, uint32_t int_flag);
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/* get the interrupt flags state of SDIO */
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FlagStatus sdio_interrupt_flag_get(uint32_t sdio_periph, uint32_t int_flag);
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/* clear the interrupt pending flags of SDIO */
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void sdio_interrupt_flag_clear(uint32_t sdio_periph, uint32_t int_flag);
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/* SDIO voltage switch functions */
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/* enable voltage switch */
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void sdio_voltage_switch_enable(uint32_t sdio_periph);
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/* disable voltage switch */
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void sdio_voltage_switch_disable(uint32_t sdio_periph);
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/* enable voltage switch sequence */
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void sdio_voltage_switch_sequence_enable(uint32_t sdio_periph);
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/* disable voltage switch sequence */
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void sdio_voltage_switch_sequence_disable(uint32_t sdio_periph);
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/* SDIO boot function */
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/* set boot mode */
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void sdio_boot_mode_set(uint32_t sdio_periph, uint32_t boot_mode);
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/* enbale DSM(data state machine) boot acknowledgment */
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void sdio_boot_ack_enable(uint32_t sdio_periph);
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/* disbale DSM(data state machine) boot acknowledgment */
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void sdio_boot_ack_disable(uint32_t sdio_periph);
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/* set boot ACK timeout period */
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void sdio_boot_acktimeout_set(uint32_t sdio_periph, uint32_t timeout);
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/* enable boot operation */
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void sdio_boot_enable(uint32_t sdio_periph);
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/* disable boot operation */
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void sdio_boot_disable(uint32_t sdio_periph);
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#endif /* GD32H7XX_SDIO_H */
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